DE-112023006744-T5 - Display substrate and display device

DE112023006744T5DE 112023006744 T5DE112023006744 T5DE 112023006744T5DE-112023006744-T5

Abstract

A display substrate and a display device are provided. The display substrate comprises a base substrate, a plurality of subpixels, and a first scanning line. The subpixel comprises a subpixel driver circuit with a driver transistor and a compensation transistor, wherein a gate electrode of the compensation transistor is coupled to a corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor. The compensation transistor comprises a compensation active layer, the compensation active layer comprising a first channel section, a second channel section, and a first conductor section, the first conductor section being coupled to both the first channel section and the second channel section. at least part of an orthographic projection of the first conductor section on the base substrate lies between an orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate.

Inventors

Wenhui GAO
Ming Hu
Miao Wang
Cong Liu
Dan Cao
Binyan Wang
Yonglin GUO
Gukhwan SONG
ZhiLiang Jiang
Yangpeng WANG

Assignees

BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Dates

Publication Date: 20260513
Application Date: 20230731

Claims (20)

Display substrate comprising: a base substrate, a plurality of subpixels, and a first scanning line, both arranged on the base substrate, the first scanning line comprising at least one section extending along a first direction, and the subpixel comprising a subpixel driver circuit comprising a driver transistor and a compensation transistor, wherein a gate electrode of the compensation transistor is coupled to a corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor; the compensation transistor comprising a compensation active layer, the compensation active layer comprising a first channel section, a second channel section, and a first conductor section, the first conductor section being coupled to the first channel section and the second channel section, respectively; at least part of an orthographic projection of the first conductor section on the base substrate is located between an orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate.
Display substrate according to Claim 1 , wherein the compensation transistor comprises a first compensation gate electrode and a second compensation gate electrode, an orthographic projection of the first compensation gate electrode on the base substrate covers the orthographic projection of the first channel section on the base substrate, an orthographic projection of the second compensation gate electrode on the base substrate covers the orthographic projection of the second channel section on the base substrate; the first compensation gate electrode is coupled to the corresponding first scanning line, and at least a portion of the first compensation gate electrode is located between the first scanning line to which the first compensation gate electrode is coupled and the gate electrode of the driver transistors, the first scanning line being multiplexed as the second compensation gate electrode.
Display substrate according to Claim 1 , wherein the display substrate further comprises a data line and a second sampling line, the second sampling line comprising at least one section extending along the first direction, the subpixel driver circuit further comprising a data write transistor, a gate electrode of the data write transistor coupled to a corresponding second sampling line, a first electrode of the data write transistor coupled to a corresponding data line, and a second electrode of the data write transistor coupled to the first electrode of the driver transistor; in an equal subpixel, the gate electrode of the data write transistor is located on a side of the first sampling line facing the gate electrode of the driver transistor.
Display substrate according to Claim 3 , wherein the data write transistor comprises a data active layer, and the gate electrode of the data write transistor comprises a gate electrode body section and a gate electrode extension section coupled together, wherein an orthographic projection of the gate electrode body section on the base substrate overlaps at least partially with an orthographic projection of the data active layer on the base substrate, the gate electrode extension section being coupled to the corresponding second scanning line; the gate electrode body section and the gate electrode of the driver transistor are arranged along the first direction, and at least a portion of the gate electrode extension section and the gate electrode of the driver transistor are arranged along a second direction, the first direction intersecting the second direction; the gate electrode body section and the gate electrode extension section are arranged in the same layer or in different layers.
Display substrate according to Claim 3 , wherein the subpixel driver circuit further comprises a first conductive interconnect and a first reset transistor, and a first end of the conductive interconnect with the The gate electrode of the driver transistor is coupled, and a second end of the first conductive connection section is coupled to the second electrode of the first reset transistor; the second scanning line is arranged at least partially around the second end of the first conductive connection section.
Display substrate according to Claim 5 , wherein the gate electrode of the data write transistor and the first scanning line are arranged in the same layer and are made of the same material, and the second scanning line and the first scanning line are arranged in different layers, wherein the second scanning line and the first conductive connecting section are arranged in the same layer and are made of the same material.
Display substrate according to Claim 5 , wherein the second scanning line comprises a plurality of straight edge sections and a plurality of curved edge sections, the straight edge section and the curved edge section being arranged alternately along the first direction, the curved edge section being arranged around the second end of the first conductive connecting section, the straight edge section comprising a protruding end, at least a part of an orthographic projection of the protruding end onto the base substrate and the orthographic projection of the gate electrode of the driver transistor onto the base substrate being arranged along the second direction, and the protruding end being coupled to the gate electrode of the data write transistor.
Display substrate according to Claim 5 , wherein the display substrate further comprises a first initialization signal line, wherein the first initialization signal line includes at least one section extending along the second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line; the orthographic projection of the first initialization signal line on the base substrate is located between the orthographic projection of the gate electrode of the driver transistor on the base substrate and the orthographic projection of the data line on the base substrate.
Display substrate according to Claim 8 , wherein the display substrate further comprises a power line, wherein the first initialization signal line, the power line and the data line are arranged in the same layer and are made of the same material, and wherein the first initialization signal line is located between the power line and the data line.
Display substrate according to Claim 5 , wherein the display substrate further comprises a second initialization signal line, a third initialization signal line, and a third sampling line, the third sampling line comprising at least one section extending along the first direction; the subpixel also comprises a light-emitting element; the subpixel driver circuit further comprises a second reset transistor and a third reset transistor, wherein a gate electrode of the second reset transistor and a gate electrode of the third reset transistor are both coupled to a corresponding identical third sampling line; a first electrode of the second reset transistor is coupled to the second initialization signal line, a second electrode of the second reset transistor is coupled to an anode of the light-emitting element; a first electrode of the third reset transistor is coupled to the third initialization signal line, a second electrode of the third reset transistor is coupled to the first electrode of the driver transistor.
Display substrate according to Claim 10 , wherein the second scanning line and the first scanning line are arranged in different layers, and the orthographic projection of the second scanning line on the base substrate overlaps at least partially with the orthographic projection of the first scanning line on the base substrate; the display substrate comprises a second gate metal layer and a first source-drain metal layer, wherein the second initialization signal line and the first source-drain metal layer are arranged in the same layer and are made of the same material, and the third initialization signal line and the second gate metal layer are arranged in the same layer and are made of the same material.
Display substrate according to Claim 10 , wherein the display substrate further comprises a current line; the first reset transistor comprises a first reset active layer, and the first reset active layer comprises a third channel section, a fourth channel section, and a second conductor section, the second conductor section being coupled to the third channel section and the fourth channel section respectively; an orthographic projection of the second conductor section on the base substrate overlaps at least partially with an orthographic projection of the second initialization signal line on the base substrate; and/or the orthographic projection of the second conductor section on the base substrate overlaps at least partially with an orthographic projection of the third initialization signal line on the base substrate; and/or the orthographic projection of the second conductor section on the base The substrate overlaps at least partially with an orthographic projection of the power line onto the base substrate.
Display substrate according to Claim 1 , wherein the display substrate further comprises a current line and a first conductive interconnect section, wherein a first end of the first conductive interconnect section is coupled to the gate electrode of the driver transistor, and a second end of the first conductive interconnect section is coupled to the second electrode of the compensation transistor; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding current line; the compensation active layer further comprises a conductor extension section coupled to the first conductor section, and an orthographic projection of the conductor extension section on the base substrate overlaps at least partially with an orthographic projection of the second electrode plate on the base substrate; and/or an orthographic projection of the first conductor section on the base substrate does not overlap with an orthographic projection of the first conductive connection section on the base substrate; and/or the orthographic projection of the second electrode plate on the base substrate overlaps at least partially with the orthographic projection of the first conductor section on the base substrate.
Display substrate according to Claim 1 , wherein the display substrate further comprises a light-shielding layer and an orthographic projection of the light-shielding layer on the base substrate overlaps at least partially with the orthographic projection of the active layer of the driver transistor on the base substrate, overlaps at least partially with the orthographic projection of the compensation active layer on the base substrate.
Display substrate according to Claim 1 , wherein the subpixel further comprises a light-emitting element, and the light-emitting element comprises an anode; the subpixel driver circuit further comprises a light emission control transistor and the second conductive interconnect section, wherein a first electrode of the light emission control transistor is coupled to the second electrode of the driver transistor, a first end of the second conductive interconnect section is coupled to a second electrode of the light emission control transistor, and a second end of the second conductive interconnect section is coupled to the anode via a first through-hole; the subpixel further comprises a pixel opening region, and an orthographic projection of the pixel opening region on the base substrate does not overlap with an orthographic projection of the first through-hole on the base substrate.
Display substrate according to Claim 1 , wherein the subpixels further comprise a light-emitting element, and the light-emitting element comprises an anode; the anode of at least some of the subpixels comprises an anode body section and an anode dummy section; an orthographic projection of the anode body section on the base substrate overlaps at least partially with an orthographic projection of the compensation active layer on the base substrate that is contained in the subpixel to which the anode body section belongs; an orthographic projection of the anode dummy section on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer on the base substrate that is contained in the subpixel that is adjacent to the anode dummy section along the first direction.
Display substrate according to Claim 16 , wherein the display substrate comprises red subpixels, green subpixels and blue subpixels; at least a portion of the subpixels comprises red subpixels and blue subpixels, and the adjacent subpixels comprise green subpixels.
Display substrate comprising: a base substrate and a plurality of subpixels, a second scanning line and a data line, all arranged on the base substrate; wherein the second scanning line comprises at least one section extending along a first direction, the subpixel comprises a subpixel driver circuit, the subpixel driver circuit comprises a first conductive link section, a driver transistor, a compensation transistor and a data write transistor; a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled via the first conductive link section to a gate electrode of the driver transistor; the compensation transistor comprises a compensation active layer, the compensation active layer comprises a first channel section, a second channel section and a first conductor section, the first conductor section being coupled to the first channel section and the second channel section, respectively; at least part of an orthographic projection of the first conductor section on the base substrate lies between an orthographic projection of the second scanning line on the base substrate and an orthographic projection the gate electrode of the driver transistor is located on the base substrate; a gate electrode of the data write transistor is coupled to a corresponding second sampling line, a first electrode of the data write transistor is coupled to a corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor; at least a part of the second sampling line is arranged around one end of the first conductive connection section.
Display substrate according to Claim 18 , wherein the display substrate further comprises a power line; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second electrode plate on the base substrate overlaps at least partially with an orthographic projection of the first conductor section on the base substrate; and/or the orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the first conductive interconnect section on the base substrate.
Display substrate according to Claim 18 , wherein the display substrate further comprises a power line; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second electrode plate on the base substrate overlaps at least partially with an orthographic projection of the first conductor section on the base substrate; and/or the orthographic projection of the first conductor section on the base substrate does not overlap with an orthographic projection of the first conductive interconnect section on the base substrate; and/or the orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the power line on the base substrate.

Description

AREA OF TECHNOLOGY The present disclosure relates to the field of display technology, in particular a display substrate and a display device. BACKGROUND With the continuous development of display technology, the demands and expectations placed on smart terminal display devices in the current market are constantly increasing, as is the average daily usage time and frequency of these devices. Currently, smart terminal display devices primarily utilize display technologies such as liquid crystal displays (LCDs) and OLEDs (organic light-emitting diodes). OLED technology offers advantageous properties such as fast response times, wide viewing angles, thinness, and light weight. Therefore, OLED technology is increasingly being used in smart terminal display devices. SUMMARY In one aspect, the present disclosure aims to provide a display substrate and a display device. To achieve the objective, the present disclosure offers the following technical solution. In a first aspect, an embodiment of the present disclosure provides a display substrate comprising a base substrate, a plurality of subpixels, and a first scanning line, both of which are arranged on the base substrate, wherein the first scanning line comprises at least a portion extending along a first direction, and the subpixel comprises a subpixel driver circuit comprising a driver transistor and a compensation transistor, wherein a gate electrode of the compensation transistor is coupled to a corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor; the compensation transistor comprises a compensation active layer, the compensation active layer comprising a first channel section, a second channel section, and a first conductor section, wherein the first conductor section is coupled to the first channel section and the second channel section, respectively; at least part of an orthographic projection of the first conductor section on the base substrate is located between an orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate. Optionally, the compensation transistor comprises a first compensation gate electrode and a second compensation gate electrode, wherein an orthographic projection of the first compensation gate electrode on the base substrate covers the orthographic projection of the first channel section on the base substrate, and an orthographic projection of the second compensation gate electrode on the base substrate covers the orthographic projection of the second channel section on the base substrate; the first compensation gate electrode is coupled to the corresponding first scanning line, and at least a portion of the first compensation gate electrode is located between the first scanning line to which the first compensation gate electrode is coupled and the gate electrode of the driver transistors, wherein the first scanning line is multiplexed as the second compensation gate electrode. Optionally, the display substrate further comprises a data line and a second sampling line, wherein the second sampling line includes at least a portion extending along the first direction, wherein the subpixel driver circuit further comprises a data write transistor, wherein a gate electrode of the data write transistor is coupled to a corresponding second sampling line, wherein a first electrode of the data write transistor is coupled to a corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor; in an identical subpixel, the gate electrode of the data write transistor is located on one side of the first sampling line facing the gate electrode of the driver transistor. Optionally, the data write transistor includes a data active layer, and the gate electrode of the data write transistor comprises a gate electrode body section and a gate electrode extension section coupled together, wherein an orthographic projection of the gate electrode body section on the base substrate overlaps at least partially with an orthographic projection of the data active layer on the base substrate, the gate electrode extension section being coupled to the corresponding second scanning line; the gate electrode body section and the gate electrode of the driver transistor are aligned along the first direction arranged, and at least a part of the gate electrode extension section and the gate electrode of the driver transistor are arranged along a second direction, and the first direction intersects the second direction; the gate electrode body section and the gate electrode extension section are arranged in the same layer or in different layers. Optionally, the subpixel driver circuit further co