DE-112024003033-T5 - Semiconductor device, semiconductor module and wireless communication device

DE112024003033T5DE 112024003033 T5DE112024003033 T5DE 112024003033T5DE-112024003033-T5

Abstract

A first semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer provided on a surface side of the substrate and comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, and comprising a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor; an intermediate layer provided in the barrier layer and comprising a semiconductor material having an etch rate lower than the etch rate of the barrier layer; a gate electrode provided on a side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being arranged between the drain electrode and the source electrode; and a recess provided between the gate electrode and the drain electrode, extending from the side of the second surface of the barrier layer to the intermediate layer.

Inventors

SAITO TATSUMA

Assignees

SONY SEMICONDUCTOR SOLUTIONS CORP

Dates

Publication Date: 20260507
Application Date: 20240619
Priority Date: 20230720

Claims (20)

A semiconductor device comprising: a substrate; a channel layer provided on a surface side of the substrate, comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, comprising a second nitride semiconductor with a band gap larger than that of the first nitride semiconductor; an intermediate layer provided within the barrier layer, comprising a semiconductor material with an etch rate lower than that of the barrier layer; a gate electrode provided on a side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being positioned between the drain electrode and the source electrode; and a recess provided between the gate electrode and the drain electrode, extending from the side of the second surface of the barrier layer to the intermediate layer.
Semiconductor device according to Claim 1 , wherein the intermediate layer is exposed on the bottom of the recess, and the thickness of the intermediate layer exposed on the bottom of the recess is less than the thickness of the intermediate layer covered by the barrier layer.
Semiconductor device according to Claim 1 , wherein the intermediate layer has a thickness greater than or equal to the thickness of an atomic layer.
Semiconductor device according to Claim 1 , where a ratio between a first thickness and a second thickness satisfies a relationship of 0.025 < first thickness/second thickness < 1.0, where the first thickness is a thickness of the barrier layer directly below the recess between the gate electrode and the drain electrode, and the second thickness is a thickness of the barrier layer between the gate electrode and the source electrode.
Semiconductor device according to Claim 1 , with the recess being provided closer to the gate electrode.
Semiconductor device according to Claim 1 , wherein a first end part of the recess on one side of the gate electrode coincides with a side surface of the gate electrode or is arranged offset from the side surface of the gate electrode towards one side of the drain electrode, and a second end part of the recess on the side of the drain electrode is arranged offset from a side surface of the drain electrode towards the side of the gate electrode.
Semiconductor device according to Claim 6 , where the distance between the drain electrode and the second end part of the recess is greater than the distance between the gate electrode and the first end part of the recess.
Semiconductor device according to Claim 1 , wherein the barrier layer and the intermediate layer each comprise aluminium, and the aluminium content in the intermediate layer is lower than the aluminium content in the barrier layer.
Semiconductor device according to Claim 1 , wherein the barrier layer and the intermediate layer each contain indium, and the indium content in the intermediate layer is higher than the indium content in the barrier layer.
Semiconductor device according to Claim 1 , which furthermore has a spacer layer between the channel layer and the barrier layer.
Semiconductor device according to Claim 10 , wherein the spacer layer comprises a first spacer layer and a second spacer layer stacked in that order from one side of the channel layer, and the thickness of the first spacer layer is greater than the thickness of the second spacer layer.
Semiconductor device according to Claim 1 , wherein the channel layer comprises GaN (gallium nitride).
Semiconductor device according to Claim 1 , wherein the substrate comprises at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride) or AlN (aluminum nitride).
Semiconductor device comprising: a substrate; a channel layer provided on a surface side of the substrate and comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, and comprising a second nitride semiconductor a band gap larger than the band gap of the first nitride semiconductor; an intermediate layer provided in the barrier layer comprising a semiconductor material with an etch rate lower than the etch rate of the barrier layer; a gate electrode provided on one side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being located between the drain electrode and the source electrode; and a two-dimensional electron gas layer provided near an interface between the channel layer and the barrier layer, comprising a low-electron gas region between the gate electrode and the drain electrode, the low-electron gas region having an electron gas concentration lower than the electron gas concentration between the gate electrode and the source electrode.
Semiconductor device according to Claim 14 , which furthermore has an insulating film between the barrier layer and the gate electrode.
Semiconductor device according to Claim 15 , where a first electron gas concentration between the gate electrode and the drain electrode and a second electron gas concentration between the gate electrode and the source electrode satisfy a relationship of 7.0E + 12 [cm -2 ] ≤ first electron gas concentration < second electron gas concentration.
Semiconductor device according to Claim 14 , where the gate electrode is formed directly on the barrier layer.
Semiconductor device according to Claim 17 , where a first electron gas concentration between the gate electrode and the drain electrode and a second electron gas concentration between the gate electrode and the source electrode satisfy a relationship of 5.0E + 12 [cm -2 ] ≤ first electron gas concentration < second electron gas concentration.
A semiconductor module comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer provided on a surface side of the substrate, comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, comprising a second nitride semiconductor with a band gap larger than the band gap of the first nitride semiconductor; an intermediate layer provided in the barrier layer, comprising a semiconductor material with an etch rate lower than the etch rate of the barrier layer; a gate electrode provided on a side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being located between the drain electrode and the source electrode; and a recess provided between the gate electrode and the source electrode, extending from the side of the second surface of the barrier layer to the intermediate layer.
Wireless communication device comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer provided on a surface side of the substrate, comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, comprising a second nitride semiconductor with a band gap larger than the band gap of the first nitride semiconductor; an intermediate layer provided in the barrier layer, comprising a semiconductor material with an etch rate lower than the etch rate of the barrier layer; a gate electrode provided on a side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being located between the drain electrode and the source electrode; and a recess provided between the gate electrode and the source electrode, extending from the side of the second surface of the barrier layer to the intermediate layer.

Description

Technical field The present disclosure relates to a semiconductor device, a semiconductor module and a wireless communication device. State of the art For example, PTL 1 discloses a semiconductor device in which a recess is formed on a channel layer from a bottom side of a gate electrode to a side of a drain electrode. Citation list Patent literature PTL 1: Japanese Disclosure Document No. 2003-59947 Summary of the invention Furthermore, it is desirable to improve a device property in a HEMT. It is desirable to provide a semiconductor device, a semiconductor module, and a wireless communication device that makes it possible to improve a device property. A first semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer provided on a surface side of the substrate and comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, and comprising a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor; an intermediate layer provided in the barrier layer and comprising a semiconductor material having an etch rate lower than the etch rate of the barrier layer; a gate electrode provided on a side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being arranged between the drain electrode and the source electrode; and a recess provided between the gate electrode and the drain electrode, extending from the side of the second surface of the barrier layer to the intermediate layer. A semiconductor module according to an embodiment of the present disclosure comprises the first semiconductor device according to the embodiment of the present disclosure described above. A wireless communication device according to an embodiment of the present disclosure comprises the first semiconductor device according to the embodiment of the present disclosure described above. A second semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer provided on a surface side of the substrate and comprising a first nitride semiconductor; a barrier layer provided on a side of the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface on a side opposite the first surface, and comprising a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor; an intermediate layer provided in the barrier layer and comprising a semiconductor material having an etch rate lower than the etch rate of the barrier layer; a gate electrode provided on a side of the second surface of the barrier layer; a drain electrode and a source electrode provided on the side of the second surface of the barrier layer, the gate electrode being arranged between the drain electrode and the source electrode; and a two-dimensional electron gas layer provided near an interface between the channel layer and the barrier layer, comprising a low-electron gas region between the gate electrode and the drain electrode, wherein the low-electron gas region has an electron gas concentration that is lower than an electron gas concentration between the gate electrode and the source electrode. In each of the first semiconductor device according to the embodiment of the present disclosure, the second semiconductor device according to the embodiment of the present disclosure, the semiconductor module according to the embodiment of the present disclosure, and the wireless communication device according to the embodiment of the present disclosure, the intermediate layer is provided in the barrier layer, and the recess is provided between the gate electrode and the drain electrode. The barrier layer is stacked on the channel layer, which comprises the first nitride semiconductor, and includes the second nitride semiconductor with a band gap larger than that of the first nitride semiconductor. The intermediate layer comprises the Semiconductor material with an etch rate lower than that of the barrier layer. The recess extends from the surface (secondary surface) of the barrier layer to the intermediate layer. The secondary surface of the barrier layer is located on the side opposite the surface of the barrier layer, which faces the channel layer. The two-dimensional electron gas layer is formed near the interface between the channel layer and the barrier layer. In this configuration, the electron gas concentration between the gate and drain electrodes is lower than the electron gas concentration between the gate and source electrodes. This reduces parasitic capacitance between the gate and drain electrodes without damaging the barrier layer. Brief description of