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EP-3276829-B1 - FREQUENCY DIVISION CORRECTION CIRCUIT, RECEPTION CIRCUIT, AND INTEGRATED CIRCUIT

EP3276829B1EP 3276829 B1EP3276829 B1EP 3276829B1EP-3276829-B1

Inventors

  • MATSUDA, ATSUSHI

Dates

Publication Date
20260506
Application Date
20170721

Claims (9)

  1. A frequency division correction circuit comprising: a first frequency divider (302) configured to perform decimal frequency division on an input signal in that the decimal frequency division is a frequency division using a non-integer number expressed by using a number after the decimal point, such as 1.5, as a frequency division ratio and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector (303) configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal, characterised in that the corrector (303) includes: a delay circuit (931, 932, 933; 941, 942, 943) configured to generate a delay signal of the first frequency division signal; and a first output circuit configured to output the first output signal on the basis of the first frequency division signal, the second frequency division signal, and the delay signal of the first frequency division signal, wherein the delay circuit (931, 932, 933; 941, 942, 943) is configured to generate a plurality of the delay signals which are different in delay time from one another with respect to the first frequency division signal; and wherein the first output circuit includes: a first p-channel field-effect transistor (601) having a gate connected to a node of the first frequency division signal, and a drain connected to a node of the first output signal; a first n-channel field-effect transistor (602) having a gate connected to a node of the second frequency division signal, and a drain connected to a node of the first output signal; and a second p-channel field-effect transistor (700) having a gate connected to a node of a first potential, a source connected to a node of a second potential, and a drain connected to a source of the first p-channel field-effect transistor; a plurality of further p-channel field-effect transistors (701, 702, 703), each of which having a gate connected to a corresponding node of the delay signals, a source connected to the node of the second potential, and a drain connected to the source of the first p-channel field-effect transistor; a second n-channel field-effect transistor (710) having a gate connected to the node of the second potential, a source connected to the node of the first potential, and a drain connected to a source of the first n-channel field-effect transistor; and a plurality of further n-channel field-effect transistors (711, 712, 713), each of which having a gate connected to a corresponding node of the delay signal, a source connected to the node of the first potential, and a drain connected to the source of the first n-channel field-effect transistor.
  2. The frequency division correction circuit according to claim 1, wherein the first frequency divider (302) is configured to output a third frequency division signal that is a logical inversion signal of the first frequency division signal and a fourth frequency division signal that is a logical inversion signal of the second frequency division signal; and the corrector (303) is configured to generate a second output signal having an intermediate duty ratio between a duty ratio of the third frequency division signal and a duty ratio of the fourth frequency division signal, based on the third frequency division signal and the fourth frequency division signal.
  3. The frequency division correction circuit according to claim 2, wherein the corrector (303) further includes: a second output circuit (900, 901, 902, 903, 910, 911, 912, 913, 921, 922) configured to output the second output signal on the basis of the third frequency division signal, the fourth frequency division signal, and the delay signal of the third frequency division signal.
  4. The frequency division correction circuit according to claim 1, wherein: the plurality of delay signals include a first delay signal, a second delay signal, and a third delay signal which are different in delay time from one another with respect to the first frequency division signal; the plurality of further p-channel field-effect transistors (701, 702, 703) includes: a third p-channel field-effect transistor (702) having a gate connected to a node of the first delay signal, a source connected to the node of the second potential, and a drain connected to the source of the first p-channel field-effect transistor (601); a fourth p-channel field-effect transistor (702) having a gate connected to a node of the second delay signal, a source connected to the node of the second potential, and a drain connected to the source of the first p-channel field-effect transistor (601); a fifth p-channel field-effect transistor (703) having a gate connected to a node of the third delay signal, a source connected to the node of the second potential, and a drain connected to the source of the first p-channel field-effect transistor (601); and the plurality of further n-channel field-effect transistors (711, 712, 713) includes: a third n-channel field-effect transistor (711) having a gate connected to the node of the delay signal of the first frequency division signal, a source connected to the node of the first potential, and a drain connected to the source of the first n-channel field-effect transistor (602); a fourth n-channel field-effect transistor (712) having a gate connected to the node of the second delay signal, a source connected to the node of the first potential, and a drain connected to the source of the first n-channel field-effect transistor (602); and a fifth n-channel field-effect transistor (713) having a gate connected to the node of the third delay signal, a source connected to the node of the first potential, and a drain connected to the source of the first n-channel field-effect transistor (602).
  5. The frequency division correction circuit according to claim 4, wherein: the second output circuit (900, 901, 902, 903, 910, 911, 912, 913, 921, 922) comprises: a sixth p-channel field-effect transistor (921) having a gate connected to a node of the fourth frequency division signal, and a drain connected to a node of the second output signal; a sixth n-channel field-effect transistor (922) having a gate connected to a node of the third frequency division signal, and a drain connected to the node of the second output signal; a seventh p-channel field-effect transistor (900) having a gate connected to the node of the first potential, a source connected to the node of the second potential, and a drain connected to a source of the sixth p-channel field-effect transistor (921); an eighth p-channel field-effect transistor (901) having a gate connected to a node of the delay signal of the third frequency division signal, a source connected to the node of the second potential, and a drain connected to the source of the sixth p-channel field-effect transistor (921); a seventh n-channel field-effect transistor (910) having a gate connected to the node of the second potential, a source connected to the node of the first potential, and a drain connected to a source of the sixth n-channel field-effect transistor (922); and an eighth n-channel field-effect transistor (911) having a gate connected to the node of the delay signal of the third frequency division signal, a source connected to the node of the first potential, and a drain connected to the source of the sixth n-channel field-effect transistor (922).
  6. The frequency division correction circuit according to claim 5, wherein: the delay circuit includes: a first inverter (931) configured to logically invert the first frequency division signal; and a second inverter (941) configured to logically invert the third frequency division signal; the gate of the third p-channel field-effect transistor (702) is connected to a node of an output signal from the second inverter (941); the gate of the third n-channel field-effect transistor (711) is connected to the node of the output signal from the second inverter (941); the gate of the eighth p-channel field-effect transistor (901) is connected to a node of an output signal from the first inverter (931); and the gate of the eighth n-channel field-effect transistor (911) is connected to the node of the output signal from the first inverter (931).
  7. The frequency division correction circuit according to any one of claims 1 to 6, further comprising: a second frequency divider (304) configured to perform integer frequency division on the first output signal.
  8. A reception circuit comprising: the frequency division correction circuit (1001) according to claim 7 configured to generate the first output signal; and a receiver (1003) configured to receive data, based on output signals of the second frequency divider (304).
  9. An integrated circuit comprising: the frequency division correction circuit (1001) according to claim 7; a receiver (1003) configured to receive data, based on output signals of the second frequency divider (304); and a processing unit (1004) configured to process the data received by the receiver.

Description

FIELD The embodiments discussed herein are directed to a frequency division correction circuit, a reception circuit, and an integrated circuit. BACKGROUND A semiconductor device including a PLL circuit having a built-in VCO, a plurality of frequency dividing circuits, and a selection circuit is known (refer to Patent Document 1). The plurality of frequency dividing circuits output a plurality of 1/N-frequency division clock signals based on the output frequency of the PLL circuit, and one of them can output a frequency division output after the decimal point. The selection circuit selects one of the frequency division outputs outputted from the plurality of frequency dividing circuits by mode setting, and outputs the clock signal of a selected frequency division ratio. Besides, a clock generating circuit that frequency-divides an input clock based on frequency division ratio data is known (refer to Patent Document 2). The clock generating circuit includes a frequency division ratio identifier that identifies the frequency division ratio data as an even number, an odd number, or a decimal number, and also includes a delay device and a frequency divider. The delay device includes the number (M), corresponding to M = 9 × p + (p - 1), of delay taps so as to change the delay amount in multiple stages, while including a tap selection unit that controls the delay amount by selecting at least one of the plurality of delay taps. Note that p represents the number of digits after decimal point in the frequency division ratio data composed of a decimal number. When the frequency division ratio identifier identifies the frequency division ratio data as a decimal number, the delay device delays the input clock to generate a delay clock, and the frequency divider frequency-divides the input clock using a rise and a fall of the edge of the delay clock and using a rise and a fall of the edge of the input clock. [Patent Document 1] Japanese Laid-open Patent Publication No. 2004-056717[Patent Document 2] Japanese Laid-open Patent Publication No. 2006-268617[Patent Document 3] US 2003/034810 discloses a method and apparatus for dividing a signal's frequency by a non-integer value.[Patent Document 4] US 2013/002319 discloses a frequency divider and phase locked loop including the frequency divider.[Patent Document 5] US 2016/118962 A1 discloses a signal generating system for generating an output signal with a 50% duty cycle. However, Patent Document 1 is for generating a divide-by-1.5 divided output signal based on four-phase clocks. SUMMARY It would be desirable to provide a frequency division correction circuit, a reception circuit, and an integrated circuit, capable of generating a decimal-frequency division signal having a duty ratio of 50% without using four-phase clocks. An aspect of the invention provides a frequency division correction circuit according to claim 1. BRIEF DESCRIPTION OF DRAWINGS Fig. 1A and Fig. 1B are diagrams illustrating configuration examples of a clock generating circuit;Fig. 2A is a diagram illustrating a configuration example of a clock generating circuit, and Fig. 2B is a timing chart illustrating the operation of the clock generating circuit in Fig. 2A;Fig. 3A is a diagram illustrating a configuration example of a frequency division correction circuit according to this embodiment, and Fig. 3B is a timing chart illustrating the operation of the frequency division correction circuit in Fig. 3A;Fig. 4 is a diagram illustrating a configuration example of a divide-by-1.5 divider;Fig. 5 is a timing chart illustrating the operation of the divide-by-1.5 divider;Fig. 6A is a diagram illustrating a first configuration example of a duty cycle corrector, and Fig. 6B is a timing chart illustrating the operation of the duty cycle corrector in Fig. 6A;Fig. 7A is a diagram illustrating a second configuration example of the duty cycle corrector, and Fig. 7B is a timing chart illustrating the operation of the duty cycle corrector in Fig. 7A;Fig. 8A is a diagram illustrating a configuration example of a part of the duty cycle corrector according to the present invention, and Fig. 8B is a timing chart illustrating the operation of the duty cycle corrector in Fig. 8A;Fig. 9A to Fig. 9D are diagrams illustrating configuration examples of the duty cycle corrector according to the present invention; andFig. 10 is a diagram illustrating a configuration example of an integrated circuit according to the present invention. DESCRIPTION OF EMBODIMENTS Fig. 1A is a diagram illustrating a configuration example of a clock generating circuit using a divide-by-2 divider 103. The clock generating circuit has a voltage control oscillator (VCO) 101 and the divide-by-2 divider 103. The voltage control oscillator 101 generates, for example, clock signals each at 28 GHz by voltage control. The divide-by-2 divider 103 frequency-divides, for example, the clock signals each at 28 GHz by 2 and outputs clock signals each at 14 GHz. Fig. 1B