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EP-3376527-B1 - MASK-INTEGRATED SURFACE PROTECTION FILM

EP3376527B1EP 3376527 B1EP3376527 B1EP 3376527B1EP-3376527-B1

Inventors

  • YOKOI, HIROTOKI
  • UCHIYAMA, TOMOAKI
  • OKA, YOSHIFUMI

Dates

Publication Date
20260506
Application Date
20161107

Claims (6)

  1. A mask-integrated surface protective film (3), comprising: a substrate film (3a) composed of a thermoplastic resin; and a mask material layer (3b) composed of a thermoplastic resin provided on the substrate film (3a), wherein the mask material layer (3b) is an ethylene-vinyl acetate copolymer resin, an ethylene-methyl acrylate copolymer resin, or an ethylene-butyl acrylate copolymer resin; and wherein the thickness of the mask material layer (3b) is 50 µm or less, characterised in that the substrate film (3a) is a polystyrene resin.
  2. The mask-integrated surface protective film (3) according to Claim 1, wherein the thickness of the mask material layer (3b) is 10 µm or less.
  3. The mask-integrated surface protective film (3) according to Claim 1 or 2, which is usable for plasma dicing.
  4. A method of producing a mask-integrated surface protective film (3) , which is usable in the production of a semiconductor chip (1), comprising: forming a mask-integrated surface protective film (3), which comprises a substrate film (3a) composed of a thermoplastic resin and a mask material layer (3b) composed of a thermoplastic resin, at one time by a co-extrusion method; and the following steps (a) to (d): (a) a step of, in the state of having laminated a mask-integrated surface protective film (3) on the side of a patterned surface (2) of a semiconductor wafer (1), grinding the backing-face of the semiconductor wafer (1); laminating a wafer fixing tape (4) on the backing-face side of the ground semiconductor wafer (1); and supporting and fixing the wafer to a ring frame (F); (b) a step of, after peeling the substrate film (3a) from the mask-integrated surface protective film (3) thereby to expose the mask material layer (3b) on top, forming an opening by cutting a portion of the mask material layer (3b) corresponding to a street of the semiconductor wafer (1) with a laser; or a step of, after forming an opening at a street of the semiconductor wafer (1) by a laser cutting of a portion of the mask-integrated surface protective film (3) corresponding to the street of the semiconductor wafer (1), exposing the mask material layer (3b) on top by peeling the substrate film (3a) from the mask-integrated surface protective film (3); (c) a plasma-dicing step of segmentalizing the semiconductor wafer (1) at the street with SF 6 plasma, and thereby for singulating the semiconductor wafer (1) into semiconductor chips (7); and (d) an ashing step of removing the mask material layer (3b) with O 2 plasma; wherein the mask material layer (3b) is provided on the substrate film (3a); wherein the substrate film (3a) is a polystyrene resin; wherein the mask material layer (3b) is an ethylene-vinyl acetate copolymer resin, an ethylene-methyl acrylate copolymer resin, or an ethylene-butyl acrylate copolymer resin, and wherein the thickness of the mask material layer (3b) is 50 µm or less.
  5. The method of producing a mask-integrated surface protective film (3) according to Claim 4, wherein the lamination of the mask-integrated surface protective film (3) on the side of the patterned surface (2) of the semiconductor wafer (1) in the above-described step (a) is a heat lamination within a range of 50°C to 100°C.
  6. The method of producing a mask-integrated surface protective film (3) according to Claim 4 or 5, wherein the thickness of the mask material layer (3b) is 10 µm or less.

Description

TECHNICAL FIELD The present invention relates to a mask-integrated surface protective film. BACKGROUND ART In recent years, remarkable evolution has made on the thinning of the semiconductor chip and the downsizing of the chip. In particular, the thinning is required in the IC cards with built-in semiconductor IC chips, such as a memory card and a smart card. Further, the downsizing of the chip is required in LED or LCD driving devices and the like. With the increase in these demands from now, the needs for the thinning of the semiconductor chip and the downsizing of the chip are thought of as being increased much more. These semiconductor chips are obtained, by thinning a semiconductor wafer to a predetermined thickness in the backgrinding step, an etching step or the like, and then dividing the semiconductor wafer into individual chips through a dicing step. In this dicing step, a blade dicing method of cutting the semiconductor wafer with a dicing blade has been used. In this blade dicing method, the cutting resistance by the blade is put directly on the semiconductor wafer at the time of cutting, so that a microscopic crack (or chipping) sometimes occurs in the semiconductor chip by this cutting resistance. Occurrence of the chipping does not only deteriorate outer appearance of the semiconductor chip, but also in some cases, there is a risk that even a circuit pattern on the chip is damaged, for example, a damage of chips is occurred due to lack (or insufficiency) of the transverse strength (or deflective strength) at the time of picking up. Further, in the foregoing physical dicing step using such a blade, it is impossible to set the width of a kerf (also referred to as a scribe line or a street) which is an interval between chips to less than the thick blade width. As a result, the number (yield) of chips gotten from a sheet of wafer decreases. Further, a long time period to be taken for the processing of the wafer is also a problem. In the dicing step, use is also made of any of various kinds of methods, other than the blade dicing method. There is a DBG (i.e. dicing before grinding) method of, in view of the difficulty in carrying out the dicing after the thinning of the wafer, forming in first a groove with a predetermined thickness in the wafer, and then carrying out a grinding step, and thereby for achieving both the thinning and the singulation into chips at the same time. By using this method, the kerf width is similar to that in the blade dicing method. However, this method has the advantage that the transverse strength of the chip is increased, so that a damage of the chip can be suppressed. Further, there is a laser dicing method of carrying out a dicing step with a laser. The laser dicing method has an advantage of being able to narrow a kerf width and also to conduct the dicing in dry process. However, there is a disadvantage that a wafer surface is contaminated with a sublimate at the time of cutting with a laser. For this reason, the wafer surface sometimes necessitates being subjected to a pretreatment of protecting it with a predetermined liquid protecting material. Further, the foregoing dry process has not yet led to achievement of a complete dry process. Further, the laser dicing method allows a further speeding-up of the processing rate, compared to the blade dicing method. However, the laser dicing method remains unchanged in carrying out a processing along every one line, and therefore it takes a certain time period for producing an extremely small chip. In a case of using a wet process, such as a water-jet method of carrying out a dicing step with a water pressure, there is a possibility that a problem occurs in the material which is sensitive to a surface contamination, such as an MEMS device, a CMOS sensor, and the like. There is also a disadvantage that narrowing of a kerf width is limited, so that a chip yield is low. The stealth dicing method of forming a modifying layer with a laser in the thickness direction of the wafer, and then splitting the modifying layer by expansion to singulate the wafer, has the advantage that a kerf width can be reduced to zero and a processing can be carried out in a dry state. However, a transverse strength of the chip tends to be decreased by the thermal history at the time of forming the modifying layer. Further, silicon debris sometimes occurs at the time of splitting the modifying layer by expansion. Further, there is a risk that the collision of each adjacent chips may be bring about short (or insufficiency) of the transverse strength. Further, as a combined method of the stealth dicing and the dicing before grinding, there is a chip-singulation method corresponding to a narrow scribe width, which forms in first a modifying layer with only a predetermined width prior to the thinning, and then carrying out a grinding step from the backing-face side, thereby for achieving the thinning and the singulation into chips at the same time. This t