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EP-3393040-B1 - OSCILLATOR CIRCUIT WITH COMPARATOR DELAY CANCELATION

EP3393040B1EP 3393040 B1EP3393040 B1EP 3393040B1EP-3393040-B1

Inventors

  • MIKULIC, JOSIP
  • SCHATZBERGER, GREGOR

Dates

Publication Date
20260506
Application Date
20170418

Claims (8)

  1. An oscillator circuit, comprising: - a first integrator unit (100) with a first capacitor (110) configured to be charged at a first integration node (121), and a similar second integrator unit (200) with a second capacitor (210) configured to be charged at a second integration node (221), each integrator unit (100, 200) including switchable current sources (111, 112, 113, 211, 212, 213), - a comparator unit (330) arranged between a first switching unit (310) and a second switching unit (320), the first switching unit (310) having a first input (I1) connected to the first integration node (121), a second input (I2) connected to a reference signal (VREF), and a third input (I3) connected to the second integration node (221), the comparator unit (330) being configured to compare a signal at the first input (I1) or a signal at the third input (I3) with the reference signal (VREF), - a logic unit (400), the second switching unit (320) being connected to the logic unit (400), the logic unit (400) being configured to provide signals (C1, C2, D1, D2, E1, E2, F1, F2) controlling the first integrator unit (100), the second integrator unit (200), the first switching unit (310) and the second switching unit (320), the signals (C1, C2, D1, D2, E1, E2, F1, F2) generating a periodic operation by alternatingly activating the first integrator unit (100) and the second integrator unit (200), - a first comparator (331) and a second comparator (332) of the comparator unit (330), - a first output (O1) of the first switching unit (310) being connected to a non-inverting input of the first comparator (331) and to an inverting input of the second comparator (332), and - a second output (O2) of the first switching unit (310) being connected to an inverting input of the first comparator (331) and to a non-inverting input of the second comparator (332), - an input (I1') of the second switching unit (320), denoted as fourth input (I1'), is connected to an output of the first comparator (331), and a further input (I2') of the second switching unit (320), denoted as fifth input (I2') is connected to an output of the second comparator (332), - wherein a first integration signal (VC1) corresponds to the charging of the first capacitor (110), a second integration signal (VC2) corresponds to the charging of the second capacitor (210), and each period (T) of the periodic operation has a duration equal to the performance of - charging the first capacitor (110) with a first slew rate, while the second integration signal (VC2) is zero, until the first integration signal (VC1) exceeds the reference signal (VREF) by a predefined value, - then discharging the first capacitor (110) with the first slew rate, while the second capacitor (210) is charged with a second slew rate, which is larger than the first slew rate, until the first integration signal (VC1) has fallen below the reference signal (VREF) by a further predefined value, - then charging the second capacitor (210) with the first slew rate, while the first integration signal (VC1) is zero, until the second integration signal (VC2) exceeds the reference signal (VREF) by the predefined value, and - then discharging the second capacitor (210) with the first slew rate, while the first capacitor (110) is charged with the second slew rate, until the second integration signal (VC2) has fallen below the reference signal (VREF) by the further predefined value.
  2. The oscillator circuit of claim 1, further comprising: a first supply terminal (8) for a supply voltage (VDD) and a second supply terminal (9) for a reference potential, a first switch (101), a second switch (102), a third switch (103) and a fourth switch (104) of the first integrator unit (100), a fifth switch (201), a sixth switch (202), a seventh switch (203) and an eighth switch (204) of the second integrator unit (200), a first current source (111) connected between the first supply terminal (8) and the first switch (101), a second current source (112) connected between the first supply terminal (8) and the second switch (102), a third current source (113) connected between the second supply terminal (9) and the fourth switch (104), the first switch (101) being connected between the first current source (111) and the first integration node (121), the second switch (102) being connected between the second current source (112) and the first integration node (121), the third switch (103) being connected between the second supply terminal (9) and the first integration node (121), the fourth switch (104) being connected between the third current source (113) and the first integration node (121), a fourth current source (211) connected between the first supply terminal (8) and the fifth switch (201), a fifth current source (212) connected between the first supply terminal (8) and the sixth switch (202), a sixth current source (213) connected between the second supply terminal (9) and the eighth switch (204), the fifth switch (201) being connected between the fourth current source (211) and the second integration node (221), the sixth switch (202) being connected between the fifth current source (212) and the second integration node (221), the seventh switch (203) being connected between the second supply terminal (9) and the second integration node (221), and the eighth switch (204) being connected between the sixth current source (213) and the second integration node (221).
  3. The oscillator circuit of one of claims 1 to 2, further comprising: a ninth switch (311) between the first input (I1) and the first output (O1), a tenth switch (312) between the second input (I2) and the first output (O1), an eleventh switch (313) between the second input (I2) and the second output (O2), and a twelfth switch (314) between the third input (I3) and the second output (O2), the ninth switch (311) and the eleventh switch (313) being simultaneously opened and closed, and the tenth switch (312) and the twelfth switch (314) being simultaneously opened and closed.
  4. The oscillator circuit of claim 3, further comprising: a third output (O3) and a fourth output (O4) of the first switching unit (310), and a propagation enable signal generation circuit (318) connected to the first input (I1), the second input (I2), the third input (I3), the third output (O3) and the fourth output (O4), the propagation enable signal generation circuit (318) comparing the reference signal (VREF) at the second input (I2) with a signal at the first input (I1) and with a signal at the third input (I3).
  5. The oscillator circuit of claim 4, further comprising:a fifth output (O1'), a sixth output (O2'), a seventh output (O3') and an eighth output (O4') at the second switching unit (320), a thirteenth switch (321) between the fourth input (I1') and the seventh output (O3'), a fourteenth switch (322) between the second supply terminal and the seventh output (O3'), a fifteenth switch (323) between the first supply terminal and the sixth output (O2'), a sixteenth switch (324) between the fourth input (I1') and the sixth output (O2'), a seventeenth switch (325) between the fifth input (I2') and the fifth output (O1'), an eighteenth switch (326) between the first supply terminal and the fifth output (O1'), a nineteenth switch (327) between the second supply terminal and the eighth output (O4'), and a twentieth switch (328) between the fifth input (I2') and the eighth output (O4'), the thirteeth switch (321), the fifteenth switch (323), the seventeenth switch (325) and the nineteenth switch (327) being simultaneously opened and closed, and the fourteenth switch (322), the sixteenth switch (324), the eighteenth switch (326) and the twentieth switch (328) being simultaneously opened and closed.
  6. The oscillator circuit of one of claims 1 to 5, further comprising: a first NOR gate (411), a second NOR gate (412), a first NAND gate (413) and a second NAND gate (414) of the logic unit (400), the first NOR gate (411) being connected to the first switching unit (310) via a first inverter (415) and to the second switching unit (320), the second NOR gate (412) being connected to the first switching unit (310) via a second inverter (416) and to the second switching unit (320), and the first NAND gate (413) and the second NAND gate (414) being connected to the first switching unit (310) and to the second switching unit (320).
  7. The oscillator circuit of claim 6, further comprising: a third NOR gate (421), a fourth NOR gate (422), a first AND gate (423), a second AND gate (424), a first flip-flop (425) and a second flip-flop (426) of the logic unit (400), inputs of the first flip-flop (425) being connected to outputs of the first NOR gate (411) and the second NOR gate (412), one output of the first flip-flop (425) being connected to inputs of the fourth NOR gate (422) and the first AND gate (423), another output of the first flip-flop (425) being connected to inputs of the third NOR gate (421) and the second AND gate (424), a further input of the third NOR gate (421) being connected to an output of the first NAND gate (413) and to a further input of the first AND gate (423), a further input of the fourth NOR gate (422) being connected to an output of the second NAND gate (414) and to a further input of the second AND gate (424), outputs of the first AND gate (423) and the second AND gate (424) being connected to inputs of the second flip-flop (426), and outputs of the second flip-flop (426) being connected to the first switching unit (310) and the second switching unit (320).
  8. The oscillator circuit of claim 7, wherein the signals (C1, C2, D1, D2, E1, E2) controlling the first integrator unit (100) and the second integrator unit (200) are provided at outputs of the third NOR gate (421), the fourth NOR gate (422), the first AND gate (423), the second AND gate (424) and the first flip-flop (425), and the signals (F1, F2) controlling the first switching unit (310) and the second switching unit (320) are provided at the outputs of the second flip-flop (426).

Description

US 2010/327985 A1 describes an oscillator circuit with a charging unit comprising two capacitors, each capacitor being provided with two switches connected in series for feeding charging currents. Comparators compare the applied voltages to a reference voltage, and a flip-flop is used to control the operation of the switches. The capacitors are alternatingly loaded to generate the oscillation. US 7,474,163 B1 describes an electronic circuit comprising a first comparator having a first input offset voltage, wherein the first comparator is operatively coupled to a first sampling capacitor, a second comparator having a second input offset voltage, wherein the second comparator is operatively coupled to a second sampling capacitor, and a control circuit operatively coupled to the first comparator and the second comparator for generating alternate cycles having a first phase and a second phase. A first sampled offset voltage is stored in the first sampling capacitor during the first phase of the alternate cycles and is subtracted from the first input offset voltage during the second phase of the alternate cycles. A second sampled offset voltage is stored in the second sampling capacitor during the second phase of the alternate cycles and is subtracted from the second input offset voltage during the first phase of the alternate cycles. K. Choe et. al.: "A Precision Relaxation Oscillator with a Self-Clocked Offset-Cancellation Scheme for Implantable Biomedical SoCs", 2009 IEEE International Solid-State Circuits Conference, pp. 402, 403, 403a, describe a self-clocked offset-cancellation scheme for comparators in a relaxation oscillator, resulting in smaller frequency drifts and lower close-in phase fluctuations. WO 2015/183513 A1 discloses an RC oscillator based on a delay-free comparator. In a comparator delay cancellation circuit a plurality of current sources charge a first capacitor and a second capacitor. Charging the capacitors takes place in alternating phases, wherein during some phases the charging is at a higher rate than during some further phases of the clock pulse. A chopper couples the capacitor voltages and a reference voltage to two comparator input nodes. The combination of the delay-cancellation circuit and the chopper extracts and cancels the comparator delay in a clock pulse using a switched-capacitor technique. WO 2015/001388 discloses an oscillator circuit comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal. The oscillator provides means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator. US 2012/0182080 discloses an oscillator including a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator. JP 2014 705744 A discloses an oscillation circuit including a pulse generation section, and the pulse generation section includes a first comparator for comparing a first voltage with a reference voltage to output a first comparison result in a normal operation mode and setting a voltage at a non-inverting input terminal at the level of the reference voltage in an initialization mode, and a second comparator for comparing a second voltage with the reference voltage to output a second comparison result in the normal operation mode and setting a voltage at a non-inverting input terminal at the level of the reference voltage in the initialization mode. Figure 8 is a diagram of an oscillator circuit, which comprises a first integrator unit 100, a second integrator unit 200 and a logic unit 400. A supply voltag