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EP-3413343-B1 - METHOD FOR PRODUCING AN ELECTRONIC MODULE

EP3413343B1EP 3413343 B1EP3413343 B1EP 3413343B1EP-3413343-B1

Inventors

  • HAUER, MARC
  • BIHLER, ECKARDT
  • HELD, JOCHEN

Dates

Publication Date
20260513
Application Date
20180524

Claims (7)

  1. A method for producing an electronic module on a flexible planar circuit substrate (3) with a conductor configuration (3b) on a first substrate surface and a plurality of electronic components (5) on the opposite, second substrate surface, wherein the electronic components (5) have component contacts (5a), which are electrically connected selectively by way of vias (7) in the circuit substrate (3) and the conductor configuration (3b), wherein the circuit substrate (3) is a thermoplastic polymer and the component contacts (5a) are embedded in the second substrate surface in the region of the vias (7), and further comprising a first thermoplastic protective film (9.1) encapsulating at least one of the electronic components (5) at least on the second substrate surface., the method comprising the following steps: - providing the flexible planar circuit substrate (3) comprising the thermoplastic polymer, - producing the conductor configuration (3b) on the first substrate surface, - producing a bore pattern in accordance with the geometry of the conductor configuration (3b), - heating the components (5) that are to be placed on the second substrate surface, - placing the components (5), aligned with the bore pattern in the circuit substrate (3), on the second substrate surface with a predetermined contact pressure and hereby fusing or thermally pressing the component contacts into the second substrate surface in the region of the bore (3c), - depositing metal selectively into the bore pattern and in the surroundings of the bores (3c) from the first substrate surface in order to produce the vias (7), and - laminating the first thermoplastic protective film (9.1) on at least a part or parts of the second substrate surface.
  2. The method according to claim 1, wherein the components (5) are heated to a placement temperature in the range between 100°C and 400°C, and/or the contact pressure lies in the range between 0.05 N and 50 N.
  3. The method according to claim 1 or 2, wherein the depositing of metal in the bore pattern is performed following the fusing or thermal pressing-in of the components (5), in particular by means of an electrochemical or physical thin-film process, such as CVD or PVD.
  4. The method according to claim 3, wherein, following the metal deposition, a galvanic reinforcement of the deposited thin film is performed.
  5. The method according to any one of claims 1 to 4, further comprising laminating a second thermoplastic protective film (9.2) on at least a part or parts of the first substrate surface.
  6. The method according to any one of claims 1 to 4 or claim 5, wherein the thermoplastic protective film (9.1, 9.2) is laminated on at a temperature in the range between 100°C and 400°C, and/or the contact pressure lies in the range between 0.05 N and 50 N.
  7. The method according to one of the preceding claims, wherein the thermoplastic material of the circuit substrate, the first thermoplastic protective film (91.) or the second thermoplastic protective film (9.2) comprises at least one material from the group of liquid-crystal polymer or LCP; polyether ether ketone, or PEEK; polyetherimide or PEI.

Description

The invention relates to a method of producing an electronic module on a flexible planar circuit substrate with a conductor configuration on a first substrate surface and a plurality of electronic components on the opposite, second substrate surface, wherein the components have component contacts, which are electrically connected selectively by way of vias in the circuit substrate and the conductor configuration. The invention covers the final products of the module made by the claimed inventive method described in claim 1. Electronic modules which are constructed on planar circuit substrates with prefabricated conductor configuration, known as printed circuit boards, have for decades been indispensable in the field of electronics and electrical engineering and are the subject of constant further development. From the many developments, particular attention has been focused in recent years on what are known as system-in-package (SIP) solutions, and specifically embedded chips or chip-in-polymer arrangements. With regard to the prior art in this specific field, reference is made to L. Boettcher et al. "Embedding of Chips for System in Package realization - Technology and Applications", www.izm.fraunhofer.de, with further literature references. In the case of this technology, standard printed circuit board fittings can be used, as stated in the above publication; however, the use of circuit substrates that consist substantially of a thermoset polymer is also known. It has been found that standard printed circuit board substrates, particularly in aggressive environments (for example aggressive atmospheric environments or the body of living beings) are not chemically inert enough and/or have excessively high diffusion rates for oxygen and/or water. The fields of application of the aforesaid technology in conjunction with standard printed circuit boards are therefore limited in this respect, and alternative materials are sought. It is known here that certain thermoplastic polymers have advantageous properties in particular in respect of low diffusion rates of oxygen, water and ions; polymers of this kind, however, are not very stable when it comes to thermal lamination in the xy plane. Thus, a person skilled in the art usually does not consider circuit substrate materials of this kind due to the high stability required of the substrate when positioning many microelectronic circuits or other electronic component on an individual substrate. JP2010147331A discloses a class substrate having an electrode provided on the surface and an insulating substrate having a through-hole formed thereon. Furthermore, US 2009/0321118 A1 an electronic component embedded printed circuit board and a manufacturing method thereof. The electronic component embedded printed circuit board includes an insulating layer forming a core layer; an electronic component inserted to project a part thereof on an upper part of the insulating layer; a metallic seed layer formed on the insulating layer including a projected surface of the electronic component; a plating layer formed on the metallic seed layer; circuit patterns electrically connected to pads of the electronic component through via-holes formed on the insulating layer; and a solder resist layer which is formed on the insulating layer and has solder balls attached onto the via-holes electrically connected to the circuit patterns. Further, US 2007/0235819 A1 discloses a power semiconductor module that includes an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor. Furthermore, EP 2 469 591 A2 relates to a method of fabricating a semiconductor device package. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having a dielectric film outer surface and a first metal layer outer surface; forming a plurality of vias extending through the laminate according to a predetermined pattern; attaching one or more semiconductor device to the dielectric film outer surface such that the semiconductor device contacts one or more vias after attachment; disposing an electrically conductive layer on the first metal layer outer surface and on an inner surface of the plurality of vias to form an interconnect layer comprising the first metal layer and the electrically conductive layer; and patterning the interconnect according to a predetermined circuit configuration to form a patterned interconnect layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor