EP-3417484-B1 - SYSTEMS AND METHODS FOR IN-SITU DOPED SEMICONDUCTOR GATE ELECTRODES FOR WIDE BANDGAP SEMICONDUCTOR POWER DEVICES

Inventors

• GORCZYCA, THOMAS, BERT

Dates

Publication Date

20260513

Application Date

20170110

Claims (9)

1. A method of fabricating a gate electrode (26) of a wide bandgap power device (10), comprising: forming a semiconductor layer (28) directly over a gate dielectric layer (24) that is disposed at a surface of an epitaxial layer (16) of the wide bandgap power device (10) while using in-situ doping to dispose a plurality of dopant atoms in the semiconductor layer (28); forming a metal-containing layer (30) directly over the semiconductor layer (28); removing portions of both the semiconductor layer (28) and the metal-containing layer (30) to form the gate electrode (26) from the remaining portions of the semiconductor layer and the metal-containing layer; and subsequently annealing the semiconductor layer (28) of the gate electrode (26) to activate a plurality of dopant atoms disposed in the semiconductor layer (28) of the gate electrode (26); wherein the step of forming the semiconductor layer (28) comprises activating a semiconductor feedstock gas and wherein the step of in-situ doping comprises activating a dopant feedstock gas at the same time as activating the semiconductor feedstock gas; wherein a flow of the dopant feedstock is initially relatively low near a beginning of a deposition and is increased to a relatively high flow near an end of the deposition, or wherein the flow of the dopant feedstock is gradually increased throughout the deposition such that a doping concentration of a portion of the in-situ doped semiconductor layer (28) that is disposed nearest the gate dielectric layer (24) is less than a doping concentration of other regions of the in-situ doped semiconductor layer of the gate electrode (26).
2. The method of claim 1, wherein the wide bandgap power device (10) is a silicon carbide wide bandgap power device, wherein the semiconductor layer (28) is a polycrystalline silicon semiconductor layer, and wherein the metal-containing layer is a tantalum silicide layer.
3. The method of claim 1, wherein removing comprises selectively etching certain portions of the semiconductor layer (28) and a metal silicide strap layer without removing a substantial portion of the gate dielectric layer (24).
4. The method of claim 1, comprising reforming at least a portion of the gate dielectric (24) after removing certain portions of the semiconductor layer (28) and the metal-containing layer (30) of the gate electrode (26).
5. The method of claim 1, wherein annealing comprises heating the wide bandgap power device to at least 850 °C for at least one minute.
6. The method of claim 1, wherein annealing comprises heating the wide bandgap power device to at least 850 °C for less than 5 minutes.
7. The method of claim 1, wherein annealing comprises heating the wide bandgap power device to at least 950 °C for 3 minutes.
8. The method of claim 1, wherein annealing comprises heating the wide bandgap power device to at least 950 °C using a pulse laser anneal for a time of less than 1 second.
9. The method of claim 1, wherein annealing comprises activating the plurality of dopant atoms of the semiconductor layer while forming an ohmic contact directly over a portion of a source region and a portion of a well region disposed in the surface of the epitaxial layer of the wide bandgap power device.

Description

BACKGROUND The subject matter disclosed herein relates to a method of fabricating wide bandgap semiconductor devices, such as silicon carbide (SiC) power devices, including field transistors (e.g., MOSFET, DMOSFET, UMOSFET, VMOSFET, trench MOSFET, etc.), insulated gate bipolar transistors (IGBT), and insulated base MOS-controlled thyristors (IBMCT). This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. Semiconductor power devices are widely used throughout modern electrical systems to convert electrical power from one form to another form for consumption by a load. Many semiconductor power devices utilize various semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal-oxide-semiconductor field-effect transistor (MOSFETs), insulated gate bipolar transistors (IGBTs), and other suitable transistors) to perform their intended functions. Specifically for high-frequency, high-voltage, and/or high-current applications, wide bandgap semiconductor power devices can provide a number of advantages over other semiconductor device in terms of high temperature operation, reduced conduction and switching losses, and smaller die size. Some wide bandgap semiconductor power devices may include a sputtered or evaporated metal gate electrode. However, since metals have a tendency to migrate at high temperature, a metal gate electrode can reduce the temperature capability and the reliability of a wide bandgap semiconductor power device. As such, some wide bandgap semiconductor power devices include polycrystalline silicon (polysilicon) gate electrode. Since the gate electrode should have a relatively high conductivity, such polysilicon gate electrodes are typically doped after formation of the gate electrode, for example, via treatment with phosphoryl chloride (POCl3). However, this treatment can introduce instability into the wide bandgap semiconductor power device. For example, phosphoryl chloride treatment generally results in an accumulation of dopant atoms at the surfaces of the gate electrode, including the lower surface of the gate electrode, near the underlying gate dielectric. Additionally, this treatment can result in a portion of the phosphorus dopant atoms diffusing into the gate dielectric itself. Dopant diffusion into and around the gate dielectric can negatively affect gate to source bias leakage and time-dependent gate oxide breakdown (TDDB), which are important to the performance and the reliability of the wide bandgap semiconductor power device. Additionally, thermal annealing a device after formation of the gate dielectric can result in bulk trap sites in the gate dielectric, which can cause undesirable threshold voltage shifts during device operation. US 2013/234159 describes a semiconductor device comprising a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor compound layer. US 2009/227100 describes a method of fabricating a semiconductor device including the steps of forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film thereafter to pattern the gate electrode layer so as to form a gate electrode, comprising: and performing a thermal treatment to the gate electrode layer or the gate electrode in a mixed gas atmosphere of an oxidized gas and an inert gas. US2001/008788 A1 discloses a method of fabricating a gate electrode wherein a layer of undoped polysilicon is deposited, followed by the deposition of an in-situ doped polysilicon layer. BRIEF DESCRIPTION The invention is set out in the claims. The method of fabricating a gate electrode according to the invention is defined