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EP-3427301-B1 - INTEGRATED HIGH-SIDE DRIVER FOR P-N BIMODAL POWER DEVICE

EP3427301B1EP 3427301 B1EP3427301 B1EP 3427301B1EP-3427301-B1

Inventors

  • ZHANG, YONGXI
  • PENDHARKAR, SAMEER P.
  • HOWER, PHILIP L.
  • GIOMBANCO, SALVATORE
  • MARINO, FILIPPO
  • SRIDHAR, SEETHARAMAN

Dates

Publication Date
20260506
Application Date
20170313

Claims (2)

  1. An N-P-Lateral Double-Diffused Metal-Oxide-Semiconductor, N-P-LDMOS, device and control circuit formed on a single chip (200A, 200B, 200C), the N-P-LDMOS device and control circuit comprising: a source electrode (522), electrically coupled to an N-source (544) and a P-drain (550) of the N-P-LDMOS, and an N-gate (230; 504) for the N-P-LDMOS device that form an outer loop, the outer loop not being closed and having a first gap, the outer loop further comprising first fingers (230') on a first side of the outer loop, the first fingers extending inward from the outer loop, and said first gap being on a second, opposite side of the outer loop between first and second ends of the outer loop, the first gap being positioned opposite the first fingers; a drain electrode (520), electrically coupled to a P-Source (542) and an N-Drain (540) of the N-P-LDMOS and a P-gate (232; 512) for the N-P-LDMOS device that form an inner loop, the inner loop not being closed and having a second gap, the inner loop being enclosed within the outer loop, the inner loop comprising second fingers (232') interdigitated with the first fingers (230') and that extend outward from the inner loop to form conduction channels between the second fingers of the inner loop and the first fingers of the outer loop, the inner loop comprising the second gap between first and second ends of the inner loop, the second gap being positioned opposite the second fingers and the second gap facing the first gap; and an N-LDMOS transistor (216) comprising a source and an N-gate (216A) located in the first gap and a drain (216B) located in the second gap, wherein the drain (216B) of the N-LDMOS transistor is coupled to a P-gate pad (222) of the N-P-LDMOS device (204), which P-gate pad is located within the inner loop, the N-gate of the N-LDMOS transistor (216) is coupled to a signal input node (IN), which node is furthermore coupled to control the N-gate (504) of the N-P-LDMOS device (204), wherein the drain of the N-LDMOS transistor (216) is coupled to said drain electrode (520) either via a resistor (212) formed within the inner loop or via a depletion-mode PMOS transistor, the depletion-mode PMOS transistor having the drain coupled to the drain of the N-LDMOS transistor (216) and the gate and the source coupled to said drain electrode (520), and wherein a source of the N-LDMOS transistor (216) is coupled to one of a lower rail and a negative voltage node (V SS ) via a current source.
  2. The N-P-LDMOS device and control circuit of claim 1 wherein, when the drain of the N-LDMOS transistor (216) is coupled to said drain electrode (520) via the resistor (212), the P-gate pad (222) is further coupled to said drain electrode of the N-P-LDMOS device through a diode (214) formed within the inner loop.

Description

This relate generally to power devices, and more particularly to an integrated highside driver for a P-N bimodal power device. BACKGROUND Lateral double-diffused metal-oxide-semiconductor (LDMOS) devices are widely used in power management, smart power integrated circuits for their convenient integration. Bimodal conduction N-P-LDMOS are four-terminal devices having both an N-LDMOS and a P-LDMOS integrated together. Accordingly, these devices have two gates for P- and N-type channels, necessitating two control signals. In these power devices, the N-LDMOS requires a low voltage signal, while the P-LDMOS requires a high-voltage signal. This four-terminal device with its requirement for two separate signals cannot be used as conveniently as a conventional three-terminal power device. Also, the complexity of the double gates driver circuit can heavily impact the benefits of a bimodal N-P-LDMOS, even to the point of negating those benefits. US2010252883A1 discloses lateral high-voltage semiconductor devices with majorities of both types for conduction. Yongxi Zhang et al. 27th International Symposium on Power Semiconductor Devices & ICs (ISPSD), IEEE, Piscataway, NJ, USA, 10 May 2015, pages 61-64, discloses a RESURF P-N bimodal LDMOS suitable for high voltage power switching applications. Kong Moufu et al. IEEE Transactions on electron devices, IEEE service center, Piscataway, NJ, USA, vol. 60, no. 10, 1 October 2013, pages 3508-3514, discloses study on dual channel n-p-LDMOS power devices with three terminals. SUMMARY The invention is set out in the appended set of claims. In described examples of an integrated circuit (IC) chip, the IC chip includes: a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, an N-gate of the N-P-LDMOS device coupled to receive an input signal; and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. In described examples of an N-P-Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS) device and control circuit formed on a single chip, the N-P-LDMOS device and control circuit include: a source and an N-gate for the N-P-LDMOS device that form an outer loop comprising first fingers, the first fingers extending inward from the outer loop, and a first gap between first and second ends of the outer loop, the first gap being positioned opposite the first fingers; a drain and a P-gate for the N-P-LDMOS device that form an inner loop that is enclosed within the outer loop, the inner loop comprising second fingers that extend outward from the inner loop to form conduction channels between the second fingers of the inner loop and the first fingers of the outer loop, the inner loop further comprising a second gap between first and second ends of the inner loop, the second gap being positioned opposite the second fingers; and an N-LDMOS transistor comprising a source and an N-gate located in the first gap and a drain located in the second gap, wherein the drain of the N-LDMOS transistor is coupled to a P-gate pad of the N-P-LDMOS device that is located within the inner loop, a gate of the N-LDMOS transistor is coupled to receive a signal input to control the N-gate of the N-P-LDMOS device and a source of the N-LDMOS transistor is coupled to one of a lower rail and a negative voltage. In further described examples of an N-P-Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS) device and control circuit formed on a single chip, the N-P-LDMOS device and control circuit include: a bottom n-type region formed on a p-type substrate; a top n-type region overlying the bottom n-type region, a portion of the bottom n-type region and the top n-type region being separated by a buried p-type region; a second p-type region partially overlying the top n-type region; an n-type well that is formed adjacent a first end of the second p-type region and the top n-type region, the n-type well containing a first heavily-doped n-type region and a first heavily doped p-type region, the first heavily doped n-type region and the first heavily-doped p-type region being coupled to a drain electrode of the N-P-LDMOS device; a p-type well that is formed adjacent a second end of the second p-type region and the top n-type region, the p-type well containing a second heavily-doped n-type region and a second heavily doped p-type region, the second heavily doped n-type region and the second heavily-doped p-type region being coupled to a source electrode of the N-P-LDMOS device; a p-gate overlying a portion of the first heavily-doped p-type region, the n-type well and a portion of the second p-type region; and an n-gate overlying a portion of the second heavily-doped n-type region, the p-type well and a portion of the second p-type region; wherein the drain electrode is coupled to a drain of an N-LDMOS transistor, the N-LDMOS transistor comprising a gate coupled to receive a signal that controls an n-gate of the N-P-LDMOS