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EP-3624200-B1 - GERMANIUM-RICH NANOWIRE TRANSISTOR WITH RELAXED BUFFER LAYER

EP3624200B1EP 3624200 B1EP3624200 B1EP 3624200B1EP-3624200-B1

Inventors

  • GLASS, GLENN
  • MURTHY, ANAND
  • BOMBERGER, Cory
  • GHANI, TAHIR
  • KAVALIEROS, JACK
  • CHOUKSEY, Siddarth
  • SUNG, SEUNG HOON
  • GUHA, BISWAJEET
  • AGRAWAL, ASHISH

Dates

Publication Date
20260506
Application Date
20190628

Claims (2)

  1. A method of fabricating a nanowire transistor, the method comprising: providing a substrate (110) comprising monocrystalline silicon; forming on the substrate (110) a layer of buffer material (112) with a thickness less than 200 nm, the layer of buffer material (112) comprising silicon and germanium with germanium from 20 to 45 atomic percent and having a lattice structure that is at least 75% relaxed relative to the substrate (110); forming a layer stack over the layer buffer material (112), the layer stack including alternating layers of a first material (136) comprising silicon and a second material (138) comprising silicon and germanium, wherein the second material contains germanium in an amount from 30 to 85 atomic percent; etching the layer stack to define one or more fins (160); forming a dummy gate structure (140) including a dummy gate electrode (142) on a channel region (130) of the fins (160); recessing source and drain regions (120) of the fins (160) and exposing the first material and the second material in the channel region (130); forming a source and drain region (120) on top of the buffer structure, the source and drain region (120) comprising a Ge-rich end portion (124) with up to 100% Ge at the interface with the exposed first material and second material in the channel region (130) and a body portion (122), the Ge-rich end portion (124) is between the channel region (130) and the body portion (122) of the source and drain region (120) and the Ge concentration gradually decreases along the end portion (124) moving away from the channel region (130) and towards the body portion (122) of the source and drain region (120), and wherein the Ge-rich end portion (124) has a lateral thickness measured between the body portion (122) and the channel region (130); removing the dummy gate electrode (142) to expose the channel region (130); selectively etching the first material to release nanowires (132) of the second material in the channel region (130) between the source region and the drain region; and forming a gate structure that is wrapped around the nanowires (132), the gate structure including a gate electrode and a gate dielectric (144) between each of the nanowires (132) and the gate electrode.
  2. The method of claim 1 further comprising: depositing on the layer of buffer material (112) an additional layer of buffer material, the additional layer of buffer material comprising silicon and germanium and having a germanium concentration greater than the layer of buffer material (112).

Description

BACKGROUND Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow between the source and drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device, and in instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate and the channel. MOSFETs may also be known as metal-insulator-semiconductor FETs (MISFETSs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) devices to implement logic gates and other digital circuits. A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations includes three different planer regions of the fin (e.g., top and two sides), such a FinFET design is sometimes referred to as a tri-gate transistor. A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region with the gate in contact with three sides of the fin, one or more nanowires extend between the source and the drain regions. In nanowire transistors the gate material generally surrounds or encircles each nanowire (hence, gate-all-around). Document US 2018/0047832 A1 discloses a method for forming a nanowire transistor device. The method includes, prior to forming source/drain regions, etching a sacrificial material such that an end of a nanowire in a channel region forms a recess within a gate structure surrounding the channel region. An extension region is then formed in the recess, in contact with the nanowire in the channel region. The extension region comprises an extension material having a different composition from a nanowire material in the channel region, thereby inducing strain. A source/drain region is subsequently formed in contact with the extension region. Nanowire transistor devices and methods for manufacturing thereof are also known from the documents US 2016/0104799 A1 and US 2018/0151452 A1. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1A illustrates a cross-sectional view taken through a channel of a nanowire transistor structure with a relaxed buffer material on the substrate below the source and drain and defects propagating into the substrate from the interface with the relaxed buffer material, in accordance with an example useful for understanding the present invention.FIGURE 1B illustrates a cross-sectional view taken through a gate electrode of the nanowire transistor structure of FIG. 1A and shows shallow trench isolation material in trenches extending into the substrate between adjacent devices, in accordance with an example useful for understanding the present invention.FIGURE 2A illustrates a cross-sectional view taken through a channel of a nanowire transistor structure with a layer of isolation material between the source/drain and the relaxed buffer material, in accordance with an example useful for understanding the present invention.FIGURE 2B illustrates a cross-sectional view taken through a gate electrode of the nanowire transistor structure of FIG. 2A, in accordance with an example useful for understanding the present invention.FIGURE 3A illustrates a cross-sectional view taken through a channel of a nanowire transistor structure, in accordance with another example useful for understanding the present invention.FIGURE 3B illustrates a cross-sectional view taken through a gate electrode of the nanowire transistor structure of FIG. 3A, in accordance with an example useful for understanding the present invention.FIGURE 4A illustrates a cross-sectional view taken through a channel of a nanowire transistor structure and shows source/drain regions that include an end portion with a different composition adjacent the gate structure. The nanowire transistor structure is not claimed but it may be fabricated through implementation of a method according to the present inventio