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EP-3624337-B1 - CONTROL CIRCUIT WITH BYPASS FUNCTION

EP3624337B1EP 3624337 B1EP3624337 B1EP 3624337B1EP-3624337-B1

Inventors

  • CHEN, CHIH-SHENG
  • LIN, JHAO-YI
  • HSU, CHING-WEN

Dates

Publication Date
20260506
Application Date
20190820

Claims (13)

  1. A control circuit (100, 400, 600, 800) with a bypass function, the control circuit (100, 400, 600, 800) comprising: a first signal terminal (N1) configured to receive a first signal (S1); a second signal terminal (N2) configured to receive a second signal (S2); an output terminal (N opt ) configured to output the first signal (S1) or the second signal (S2); a first switch unit (110) comprising a first terminal coupled to the first signal terminal (N1), and a second terminal; a second switch unit (120) comprising a first terminal coupled to the second terminal of the first switch unit (110), and a second terminal; a third switch unit (130) comprising a first terminal coupled to the second signal terminal (N2), and a second terminal; a first output switch unit (150) comprising a first terminal coupled to the second terminal of the second switch unit (120), and a second terminal coupled to the output terminal (N opt ); a fourth switch unit (140) comprising a first terminal coupled to the second terminal of the third switch unit (130), and a second terminal coupled to the first terminal of the first output switch unit (150); and a first bypass unit (180) comprising a first terminal coupled to the second terminal of the first switch unit (110), and a second terminal coupled to the output terminal (N opt ) and the second terminal of the first output switch unit (150), wherein the first bypass unit (180) is configured to provide a first bypass path (Ptb1) for bypassing the first signal (S1); each of the first switch unit (110), the second switch unit (120), the third switch unit (130), the fourth switch unit (140) and the first bypass unit (180) includes at least a transistor with a respective control terminal to receive a respective control voltage for being either turned on or turned off; and the control circuit (100, 400, 600, 800) being characterised in that : the output terminal (N opt ) is coupled to an amplification circuit (615) and a bypass circuit (625), wherein in a first operation mode, the first switch unit (110) and the bypass unit (180) are configured to be turned on, and the second switch unit (120), the third switch unit (130), the fourth switch unit (140) and the output switch unit (150) are configured to be turned off, so that the first signal (S1) is bypassed through the bypass unit (180), and outputted from the output terminal (N opt ); in a second operation mode, the first switch unit (110), the second switch unit (120) and the output switch unit (150) are configured to be turned on, and the bypass unit (180), the third switch unit (130) and the fourth switch unit (140) are configured to be turned off, so that the first signal (S1) is transmitted through the first switch unit (110), the second switch unit (120) and the output switch unit (150), and outputted from the output terminal (N opt ); in a third operation mode, the third switch unit (130), the fourth switch unit (140) and the output switch unit (150) are configured to be turned on, and the first switch unit (110), the second switch unit (120) and the bypass unit (180) are configured to be turned off, so that the second signal (S2) is transmitted through the third switch unit (130), the fourth switch unit (140) and the output switch unit (150), and outputted from the output terminal (N opt ).
  2. The control circuit (100, 400, 600, 800) of claim 1 characterised in that : the first switch unit (110) and the second switch unit (120) form a first path (Pt1), the third switch unit (130) and the fourth switch unit (140) form a second path (Pt2), and the first bypass unit (180) forms the first bypass path (Ptb1).
  3. The control circuit (100, 400, 600, 800) of claim 1 or 2 characterised in that : the first switch unit (110) further comprises a control terminal configured to receive a first control signal (V1); the second switch unit (120) further comprises a control terminal configured to receive a second control signal (V2); the third switch unit (130) further comprises a control terminal configured to receive a third control signal (V3); the fourth switch unit (140) further comprises a control terminal configured to receive a fourth control signal (V4); the first bypass unit (180) further comprises a control terminal configured to receive a fifth control signal (Va); and the first output switch unit (150) further comprises a control terminal configured to receive a sixth control signal (Vc).
  4. The control circuit (100, 400, 600, 800) of any one of claims 1, 2 and 3 characterised in that : the first switch unit (110), the second switch unit (120), the third switch unit (130), the fourth switch unit (140), the first bypass unit (180) and the first output switch unit (150) respectively comprise a first transistor (M11), a second transistor (M12), a third transistor (M13), a fourth transistor (M14), a fifth transistor (M15) and a sixth transistor (M16); and a size of the third transistor (M13) is substantially equal to a size of the fourth transistor (M14), the size of the fourth transistor (M14) is not larger than a size of the sixth transistor (M16), a size of the fifth transistor (M15) is smaller than the size of the fourth transistor (M14), and the size of the fifth transistor (M15) is not larger than the size of the sixth transistor (M16).
  5. The control circuit (100, 400, 600, 800) of any one of the preceding claims characterised in that : the first bypass unit (180) comprises a transistor (M15), and the transistor (M15) comprises a first terminal coupled to the first terminal of the first bypass unit (180), a control terminal coupled to a control terminal of the first bypass unit (180), and a second terminal coupled to the second terminal of the first bypass unit (180).
  6. The control circuit (100, 400, 600, 800) of any one of the preceding claims characterised in that : the first bypass unit (180) comprises at least one capacitor (C31, C32) and a transistor (M15); the transistor (M15) comprises a first terminal, a control terminal coupled to a control terminal of the first bypass circuit (180), and a second terminal; and the at least one capacitor (C31, C32) is coupled in series between the first terminal of the transistor (M15) and the first terminal of the first bypass unit (180) or between the second terminal of the transistor (M15) and the second terminal of the first bypass unit (180).
  7. The control circuit (400, 600, 800) of any one of claims 1 and 3-6 characterised by further comprising: a second bypass unit (185) comprising a first terminal coupled to the second terminal of the third switch unit (130), and a second terminal coupled to the output terminal (N opt ), wherein the second bypass unit (185) is configured to provide a second bypass path (Ptb2) for bypassing the second signal (S2).
  8. The control circuit (600) of any one of the preceding claims characterised by further comprising: a third signal terminal (N3) configured to receive a third signal (S3); a fourth signal terminal (N4) configured to receive a fourth signal (S4); a fifth switch unit (210) comprising a first terminal coupled to the third signal terminal (N3), and a second terminal; a sixth switch unit (220) comprising a first terminal coupled to the second terminal of the fifth switch unit (210), and a second terminal; a seventh switch unit (230) comprising a first terminal coupled to the fourth signal terminal (N4), and a second terminal; an eighth switch unit (240) comprising a first terminal coupled to the second terminal of the seventh switch unit (230), and a second terminal coupled to the second terminal of the sixth switch unit (220); a second output switch unit (250) comprising a first terminal coupled to the second terminal of the eighth switch unit (240), and a second terminal coupled to the output terminal (N opt ); and a third bypass unit (280) comprising a first terminal coupled to the second terminal of the fifth switch unit (210), and a second terminal coupled to the output terminal (N opt ), wherein the third bypass unit (280) is configured to provide a third bypass path (Ptb3) for bypassing the third signal (S3); wherein the output terminal (N opt ) is further configured to output the third signal (S3) or the fourth signal (S4).
  9. The control circuit (600) of any one of the preceding claims characterised in that the output terminal (N opt ) is coupled to an amplification path unit (610) and a bypass path (620), wherein the amplification path unit (610) is further coupled to the amplification circuit (615) and the bypass path unit (620) is further coupled to the bypass circuit (625).
  10. The control circuit (600) of claim 9 characterised in that : the amplifier circuit (615) is configured to amplify a signal outputted by the output terminal (N opt ); and the bypass circuit (625) is configured to bypass a signal outputted by the output terminal (Nopt).
  11. The control circuit (600) of any one of claims 9-10 characterised in that the amplification path unit (610) comprises an amplification path switch configured to turn on or turn off the amplification path unit (610).
  12. The control circuit (600) of any one of claims 1, 2 and 3-8 characterised in that the output terminal (N opt ) is further coupled to a common path unit (710), and the common path unit (710) is further coupled to the amplification circuit (615) and the bypass circuit (625).
  13. The control circuit (600) of claim 12 characterised in that the amplification circuit (615) is configured to amplify a signal outputted by the output terminal (N opt ), and the bypass circuit (625) is configured to bypass the signal outputted by the output terminal (N opt ).

Description

Field of the Invention The disclosure relates to a control circuit, and more particularly, a control circuit with a bypass function and having a bypass path for bypassing a signal. Background of the Invention In a front-end module receiver circuit for supporting multiple frequency bands, a plurality of input terminals can be set respectively corresponding to the multiple frequency bands. For example, in a single pole multiple throw (SPMT) radio-frequency switch circuit, every input terminal can receive a signal, and the signal can be transmitted through a matching component and a set of switches, enter a node, and then be outputted. The foresaid node can be coupled to a function path and a bypass path. If a switch of the function path is turned off, the circuit can enter a bypass mode for bypassing the signal through the bypass path. Although this sort of structure is feasible, many shortcomings have been observed in practice. For example, since switches and capacitors need to be set on the function path, the size of the circuit will be enlarged and can hardly be reduced. Moreover, since each of a plurality of paths having a plurality of switches connected in series are coupled to the node, the loading effect will be excessive, and this can be disadvantageous to the efficiency of the circuit. In the bypass mode, the loading effect will be particularly significant. Furthermore, the abovementioned structure will cause higher insertion loss (IL). Reference D1 (US 2017/163297 A1) discloses a reconfigurable multiplexer, and FIG.7D of D1 teaches a circuit including switches for controlling signals. Reference D2 (US 2011/025404 A1) discloses a circuit including switches with variable control voltages, and FIG.2 of D2 teaches a circuit including switches for controlling signals. Reference D3 (US 2009/0295472 A1) discloses a switch-around low noise amplifier, and FIG.2 of D3 teaches a circuit including switches for controlling signals. Reference D4 (US 2017/033786 A1) discloses a radio frequency (RF) switch with bypass topology, and FIG.2 of D4 teaches a circuit including switches for controlling signals. Reference D5 (US 2018/226932 A1) discloses a radio frequency front end of user equipment, and FIG.9B of D5 teaches a circuit including switches for controlling signals. Reference D6 (US 2018/0048336 A1) discloses a diversity switch circuit, and FIG.5 of D6 teaches a circuit including switches for controlling signals. Summary of the Invention The present invention aims at providing a control circuit with a bypass function and having a bypass path for bypassing a signal. This is achieved by a control circuit according to claim 1 here below. The dependent claims pertain to corresponding further developments and improvements. As will be seen more clearly from the detailed description following below, the claimed control circuit is with a bypass function. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof: FIG.1 illustrates a control circuit with a bypass function according to an embodiment partially covered by the scope of protection of the claims;FIG.2 illustrates the control circuit of FIG.1 according to an embodiment partially covered by the scope of protection of the claims;FIG.3 illustrates the bypass unit of the control circuit of FIG.1 according to another embodiment partially covered by the scope of protection of the claims;FIG.4 illustrates a control circuit with a bypass function according to an embodiment partially covered by the scope of protection of the claims;FIG.5 illustrates a switch unit of the control circuit of FIG.1 according to an embodiment partially covered by the scope of protection of the claims;FIG.6 illustrates an application of a control circuit with a bypass function according to embodiment covered by the claimed invention;FIG.7 illustrates an application of the control circuit according to another embodiment covered by the claimed invention;FIG.8 illustrates a control circuit according to an embodiment partially covered by the scope of protection of the claims; andFIG.9 illustrates a capacitor equivalent structure of the circuit of FIG.8 for qualitative analysis and partially covered by the scope of protection of the claims. Hereinafter, whenever an embodiment is described, reference is to be made to the above figure list to determine whether the embodiment/example is to be read as covered by the claimed invention or as an embodiment/example/aspect which is partially covered by the claimed invention. Detailed Description Below, exemplary embodiments will be described in detail with reference to accompanying drawings so as to be easily realized by a person having ordinary knowledge in the art. The inventive concept may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity, and lik