EP-3633852-B1 - AMPLIFIER CIRCUIT

EP3633852B1EP 3633852 B1EP3633852 B1EP 3633852B1EP-3633852-B1

Inventors

CHEN, CHIH-SHENG
HSU, CHING-WEN

Dates

Publication Date: 20260513
Application Date: 20191002

Claims (1)

An amplifier circuit (1000) characterised by comprising: an output terminal (Po) configured to output an amplification signal (Sa); an amplification unit (A2) comprising: a first transistor (X1) comprising a control terminal configured to receive a first input signal (S1), a first terminal coupled to the output terminal and configured to output an amplified first input signal, and a second terminal; a second transistor (X2) comprising a control terminal configured to receive a second input signal (S2), a first terminal coupled to the output terminal and configured to output an amplified second input signal, and a second terminal; and a third transistor (Xc) coupled between the output terminal (Po) and the first transistor (X1), and coupled between the output terminal (Po) and the second transistor (X2), the third transistor (Xc) comprising a first terminal coupled to the output terminal (Po), and a second terminal; a first switch (X4) comprising a first terminal coupled to the second terminal of the third transistor (Xc), and a second terminal coupled to the first terminal of the first transistor (X1); a second switch (X6) comprising a first terminal coupled to the second terminal of the third transistor (Xc), and a second terminal coupled to the first terminal of the second transistor (X2); a third switch (X5) comprising a first terminal coupled to the first terminal of the first transistor (X1), and a second terminal coupled to a reference voltage terminal (Vr); and a fourth switch (X7) comprising a first terminal coupled to the first terminal of the second transistor (X2), and a second terminal coupled to the reference voltage terminal (Vr); wherein the amplification signal (Sa) is generated using at least the amplified first input signal and/or the amplified second input signal; wherein the first input signal (S1) is a signal of a first frequency band and the second input signal (S2) is a signal of a second frequency band.

Description

Field of the Invention The disclosure is related to an amplifier circuit, and more particularly, an amplifier circuit supporting various operation modes. Background of the Invention In the field of circuit application, amplifier circuits are often used. In an amplifier circuit, an input terminal can be used to receive an input signal, the input signal can be amplified to generate an amplified signal, and an output terminal can output the amplified signal. However, a conventional amplifier circuit can merely be used to perform signal process for a single input signal rather than supporting various operation modes. Reference D1 (US 2009/0085668 A1) discloses a circuit used for radio frequency communications. Reference D2 (US 2013/0315348 A1) discloses circuit structures with transistors coupled to one another. Reference D3 (US 2016/0204966 A1) discloses amplification units with transistors. Reference D4 (US 2005/0231290 A1) discloses structures of LNA (low noise amplifier) with coupled transistors. However, none of References D1 to D4 teaches a structure which can prevent signals leaking to unused paths. Reference D3 teaches amplification units which can reduce power consumption and enhance a noise feature. However, Reference D3 fails to disclose switches used to shunt leakage signals to a reference voltage terminal, and fails to provide solutions for improving the isolation between a path in use and an unused path and for improving the reverse isolation capability of the amplification units. US 2006119435 A1 discloses a power amplifier for wireless communication including a cascode with a first transistor receiving and amplifying an input signal, and a second transistor connected to the first transistor in series and operated by a DC bias voltage; a third transistor connected between the cascode and an output end, and operated by a dynamic gate bias and outputting a signal. A voltage divider includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor. US 2007296507 A1 discloses a cascode-connected amplifier circuit including two transistors cascode-connected to each other, and a switching element by which it is determined whether or not a collector of an input-side transistor is grounded. The amplifier circuit can provide improvement in isolation. Summary of the Invention The present invention aims at providing an amplifier circuit supporting various operation modes. This is achieved by an amplifier circuit according to claim 1 here below. As will be seen more clearly from the detailed description following below, the claimed amplifier circuit comprises an output terminal, an amplification unit, a first switch, a second switch, a third switch and a fourth switch. The amplification unit comprises a first transistor, a second transistor and a third transistor. The output terminal is configured to output an amplification signal. The first transistor comprises a control terminal configured to receive a first input signal, a first terminal coupled to the output terminal and configured to output an amplified first input signal, and a second terminal. The second transistor comprises a control terminal configured to receive a second input signal, a first terminal coupled to the output terminal and configured to output an amplified second input signal, and a second terminal. The third transistor is coupled between the output terminal and the first transistor, and coupled between the output terminal and the second transistor. The third transistor comprises a first terminal coupled to the output terminal, and a second terminal. The first switch comprises a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the first terminal of the first transistor. The second switch comprises a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the first terminal of the second transistor. The third switch comprises a first terminal coupled to the first terminal of the first transistor, and a second terminal coupled to a reference voltage terminal. The fourth switch comprises a first terminal coupled to the first terminal of the second transistor, and a second terminal coupled to the reference voltage terminal. The amplification signal is generated using at least the amplified first input signal and/or the amplified second input signal. The first input signal S1 is a signal of a first frequency band and the second input signal S2 is a signal of a second frequency band. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof: FIG.1 illustrates an amplifier circuit;FIG.2 illustrates an amplifier circuit;FIG.3 illustrates an amplifier circuit;FIG.4 illustrates an amplifier circuit;FIG.5