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EP-3635861-B1 - THREE-INPUT CONTINUOUS-TIME AMPLIFIER AND EQUALIZER FOR MULTI-LEVEL SIGNALING

EP3635861B1EP 3635861 B1EP3635861 B1EP 3635861B1EP-3635861-B1

Inventors

  • LEE, CHULKYU
  • CHOU, SHIH-WEI
  • DUAN, Ying

Dates

Publication Date
20260513
Application Date
20180510

Claims (9)

  1. A receiver equalizer (400, 450) for a three-level signaling system, comprising: a first transistor (P16) arranged in parallel with a second transistor (P17) and with a third transistor (P18), wherein a gate for the first transistor is configured to receive a first signal (AO) of three signals, a gate for the second transistor is configured to receive a second signal (BO) of three signals, and a gate for the third transistor is configured to receive a third signal (CO) of three signals; three current sources (405, 410, 415), with a first current source (405) of the three current sources configured to bias a first terminal of the first transistor (P16); a second current source (410) of the three current sources configured to bias a first terminal of the second transistor (P17); a third current source (415) of the three current sources configured to bias a first terminal of the third transistor (P18); a first equalizing pair of a capacitor and a resistor connected to the first terminal of the first transistor (P16); a second equalizing pair of a capacitor and a resistor connected to the first terminal of the second transistor (P17); and a third equalizing pair of a capacitor and a resistor connected to the first terminal of the third transistor (P18); and wherein the first equalizing pair, the second equalizing pair, and the third equalizing pair are all connected to a common node (455), wherein the common node (455) is only connected to the first equalizing pair, the second equalizing pair, and the third equalizing pair; or wherein the first equalizing pair is also connected to the first terminal of the second transistor (P17), the second equalizing pair is also connected to the first terminal of the third transistor (P18), and the third equalizing pair is also connected to the first terminal of the first transistor (P16).
  2. The receiver equalizer of claim 1, wherein the first transistor, the second transistor, and the third transistor are p-type metal oxide semiconductor, PMOS, transistors.
  3. The receiver equalizer of claim 1, further comprising: a first resistor connected to a second terminal of the first transistor; a second resistor connected to a second terminal of the second transistor; and a third resistor coupled between a second terminal of the third transistor.
  4. The receiver equalizer of claim 3, wherein the first resistor, the second resistor, and the third resistor are all connected to ground.
  5. The receiver equalizer of claim 1, wherein the first transistor is matched to the second transistor and to the third transistor.
  6. A method for a receiver equalizer (400, 450) for a three-level signaling system, comprising: weakly switching on (500) a first transistor responsive to a first input signal of three signals to produce a low output voltage at a first terminal of the first transistor; switching on (505) a second transistor responsive to a second input signal of three signals to produce a high output voltage at a first terminal of the second transistor; partially switching on (510) a third transistor responsive to a third input signal of three signals to produce a mid-range output voltage at a terminal of the third transistor, wherein the high voltage is greater than the mid-range voltage, and the mid-range voltage is greater than the low voltage; boosting (515) the high-frequency gain of the receiver equalizer with respect to a difference between the high output voltage and the low output voltage by conducting charge from a second terminal of the first transistor to a second terminal of the second transistor through a first equalizing pair of a capacitor and a resistor; boosting the high frequency gain of the receiver equalizer with respect to a difference between the mid-range output voltage and the low output voltage by conducting charge from the second terminal of the first transistor to a second terminal of the third transistor through a second equalizing pair of a capacitor and a resistor; boosting the high-frequency gain of the receiver equalizer with respect to a difference between the high output voltage and the mid-range output voltage by conducting charge from the second terminal of the third transistor to the second terminal of the second transistor through a third equalizing pair of a capacitor and a resistor; and wherein the first equalizing pair, the second equalizing pair, and the third equalizing pair are all connected to a common node (455), wherein the common node (455) is only connected to the first equalizing pair, the second equalizing pair, and the third equalizing pair; or wherein the first equalizing pair is also connected to the first terminal of the second transistor (P17), the second equalizing pair is also connected to the first terminal of the third transistor (P18), and the third equalizing pair is also connected to the first terminal of the first transistor (P16).
  7. The method of claim 6, further comprising driving a first current into the second terminal of the first transistor, wherein producing the low output voltage at the first terminal of the first transistor comprises conducting a portion of the first current through a resistor connected to the second terminal of the first transistor.
  8. The method of claim 7, further comprising: driving a second current into the second terminal of the second transistor; and driving a third current into the third terminal of the third transistor.
  9. The method of claim 6, further comprising: amplifying a trio of received signals for the three-level signaling system to produce the first input signal, the second input signal, and the third input signal.

Description

Technical Field This application relates to multi-level signaling, and more particularly to a three-input continuous-time amplifier and equalizer for multi-level signaling. Background Slow-speed transmission of multi-bit words typically occurs over multi-wire buses. For example, an eight-bit word may be transmitted over a bus having eight wires, one for each bit. But in such conventional busses, each bit propagates independently of the remaining bits. As the data rates increase, such parallel data transmission becomes problematic in that the various bits in a word become skewed from each other as the word propagates over the bus. Given the issues with skew between multiple bits in high-speed communication, various serializer/deserializer (SerDes) systems have been developed. A SerDes transmitter serializes a multi-bit word into a serial stream of corresponding bits for transmission to a receiver. There can then be no such skew between adjacent bits as occurs in parallel transmission since a single transmission line (which may be differential) is used for the serial data stream. The SerDes receiver deserializes the received serial bit stream into the original word. However, the transmission line and the receiver load introduce distortion into the serial data stream as the data transmission rate exceeds, for example, 10 GHz. Adjacent bits in the serial data stream then begin to interfere with each other. Complicated equalizing schemes become necessary to fight the resulting inter-symbol interference and thus it becomes difficult to push SerDes data transmission rates ever higher. To increase data transmission rates over the SerDes limitations, a three-level signaling protocol has been developed in which three transmitters drive three separate transmission lines. The three transmitters may be either voltage-mode or current-mode transmitters. Since the net current must be zero, all three transmitters cannot be active (either transmitting or receiving current) in a three-level signaling system. Similarly, there must be current injected and received so all three transmitters cannot be inactive for any given symbol. So that means that two of the three transmitters will be active for each symbol, with one sourcing current and the other receiving current. From a set of three transmitters, there are three distinct pairs of transmitters that can be active. Within each pair, there are two possibilities depending upon which transmitter is sourcing versus which transmitter is receiving. There are thus six distinct combinations of two active transmitters each sourcing or receiving a given amount of current in a three-transmitter multi-level system. Each distinct combination of active transmitters may be denoted as a symbol. Since there are six possible symbols, each transmitted symbol represents 2.5 bits. In this fashion, data transmission speeds may be more than doubled over binary transmission at the same symbol rate using a single channel, albeit at the cost of increased power consumption. The three transmitted signals may be designated as signals A, B, and C, respectively. The binary values of these signals depend upon a number of factors such as the power supply voltage and the termination resistances. In the following examples, the binary high voltage is assumed to be 300 mV whereas the binary low voltage is assumed to be 100 mV. The remaining signal voltage will be approximately one-half of the binary high voltage (in this example, 200 mV). However, it will be appreciated that these voltage values are merely exemplary and may be varied in alternative implementations. It is conventional to receive the three transmitted signals using three high-speed receiver equalizers. However, the amplitudes of the received signals may be too low for equalization to proceed efficiently due to propagation losses. It is thus also conventional to boost the amplitude of the received signals prior to equalization. The three received signals prior to amplification may be designated as signals A, B, and C. Received signal A would thus be amplified to form into an amplified (which may also be designated as level-shifted) signal AO. Similarly, received signal B would be amplified to form an amplified signal BO, and received signal C would be amplified to form an amplified signal CO. It is conventional to perform the amplification using three high-speed receiver amplifiers as shown in Figure 1A. A first receiver amplifier 100 includes a differential pair of PMOS transistors P1 and P2. The received signal A drives the gate of transistor P1 whereas received signal B drives the gate of transistor P2. The drains of transistors P1 and P2 couple to ground through respective resistors R. The drain of transistor P1 drives an output signal AO. Similarly, the drain of transistor P2 drives an output signal BO. A current source of I drives the sources of transistors P1 and P2. A second receiver amplifier 105 is analogous to receiver 100 in that it incl