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EP-3675164-B1 - DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FOR HIGH PERFORMANCE MICROPROCESSORS

EP3675164B1EP 3675164 B1EP3675164 B1EP 3675164B1EP-3675164-B1

Inventors

  • GOMES, WILFRED
  • BOHR, MARK T.
  • KODURI, RAJABALI
  • NEIBERG, Leonard
  • KOKER, ALTUG
  • SIVAKUMAR, SWAMINATHAN

Dates

Publication Date
20260513
Application Date
20191122

Claims (12)

  1. A die (201), comprising: a plurality of semiconductor sections (201a- 201b, 641-647); a top layer interconnect structure comprising stitching structures that connect top layer interconnects of a first semiconductor section (201a) to top layer interconnects of a second semiconductor section (201b), wherein the first semiconductor section and the second semiconductor section are sections of a monolithic base die; and at least one bridge die (221) located at an interface between a separate semiconductor section and the monolithic base die, wherein the at least one bridge die connects the separate semiconductor section to one or more semiconductor sections of the monolithic base die.
  2. The die of claim 1, wherein the stitching structures comprise stitching wires.
  3. The die of claim 1 or 2, wherein the bridge die (221) is connected above first and second semiconductor sections.
  4. The die of claim 1 or 2, wherein the bridge die (221) is connected underneath first and second semiconductor sections.
  5. The die of claim 1, 2, 3 or 4, wherein the bridge die (221) includes interconnect input/output, I/O, logic.
  6. The die of claim 1, 2, 3, 4 or 5, wherein the bridge die (221) includes a plurality of SRAM semiconductor layers.
  7. The die of claim 1, 2, 3, 4, 5 or 6, wherein the monolithic base die comprises a plurality of semiconductor sections that are separable.
  8. A method for forming a die, the method comprising: forming (621) stitching structures to connect top layer interconnects corresponding to die quadrants of sets of die quadrants on a wafer, wherein each die quadrant is a semiconductor section; singulating (623) the wafer into the sets of die quadrants; and testing (625) the singulated sets of die quadrants to determine if the quadrants of the sets of die quadrants pass testing, wherein if all of the quadrants of a set of die quadrants are identified as functional, harvesting the set of functional die quadrants on a monolithic semiconductor base die (627), and wherein if a quadrant of a set of die quadrants is identified as being non-functional, performing a second singulation and leaving the one or more functional die quadrants of the set of die quadrants as a monolithic semiconductor base die (629), and arranging at least one bridge die at an interface between a separate functional die quadrant and the monolithic semiconductor base die, wherein the at least one bridge die connects the separate functional die quadrant to one or more functional die quadrants of the monolithic semiconductor base die.
  9. The method of claim 8, wherein forming the stitching structures include forming stitch wires that connect top layer interconnects of a first die quadrant to top layer interconnects of a second die quadrant.
  10. The method of claim 8 or 9, wherein the arranging the at least one bridge die includes connecting the bridge die above the separate functional die quadrant and the one or more functional die quadrants of the monolithic semiconductor base die.
  11. The method of claim 8 or 9, wherein the arranging the one or more bridge die includes connecting the bridge die underneath the separate functional die quadrant and the one or more functional die quadrants of the monolithic semiconductor base die.
  12. The method of claim 8, 9, 10 or 11, wherein arranging the one or more bridge die includes forming an interconnect to input/output (I/O) logic.

Description

TECHNICAL FIELD The present invention pertains to providing a high yielding process for high performance microprocessors and, in particular, to a die interconnection scheme for providing a high yielding process for high performance microprocessors. BACKGROUND Fabricating high performance microprocessors in a low yielding process presents significant challenges to chip designers. High performance microprocessor architectures can include very high numbers of interconnected compute and network elements. The larger the contiguous silicon area, the greater the challenge (exponentially so) of yielding a fully functional die. The large size of the network part of high performance microprocessor architectures result in large total die area. Consequently, large size network elements are difficult to yield, especially in a relatively low yielding manufacturing process. Rapid product lifecycles and high development costs pressure manufacturing firms to cut not only their development times (time-to-market), but also the time to reach full capacity utilization (time-to-volume). The period between completion of development and full capacity utilization is known as production ramp-up. During that time, new production processes are not well understood, and contributes to low yields and low production rates. However, because of the aforementioned pressures some yield is required during early ramp-up and debug phases. Conventional approaches to addressing yield and performance in high performance microprocessor development rely upon packaging techniques or embedded bridges. These approaches come with large power and performance penalties. Accordingly, many useful high performance microprocessor architecture designs cannot be built using current approaches. US 10, 163,798 B1 discloses a bridge die 140 seated within a bridge recess of an embedded multiple-die interconnect bridge package. US 2010/0327424 A1 discloses a bridge 140 attached to sides 213 of a substrate 110. US 2017/0125396 A1 discloses a coupling point such as a stitching point between an interconnect 558a of a first base device and an interconnect 558b of a second base device. WO 2013/119309 A1 discloses a die assembly including bridge 1110 used to bridge two interposers which have a gap between them. US 2015/0008954 A1 discloses a die 200 having a first die region 211 and a second die region 212. Die region 211 and die region 212 may be coupled to one another via mask stitching region 210. Along those lines, conductors 260 may cross a border between die regions 211 and 212. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an illustration of an example graphics, server, field programmable gate array (FPGA), artificial intelligence (AI), system on chip (SOC) or other large architecture.FIG. 2A illustrates the manner in which a large architecture can be separated into computation and interconnect components according to a previous approach.FIG. 2B illustrates the manner in which a base die can be separated into a first base die section and a second base die section.FIG. 2C illustrates the manner in which a first base die section and a second base die section can be connected by a bridge die.FIG. 2D illustrates another manner in which a first base die section and a second base die section can be connected by a bridge die.FIGS. 3A-3C illustrate the formation of a top layer interconnection structure used to connect base die sections to form a functionally monolithic base die according to an embodiment.FIGS. 4A-4C illustrate the manner in which bridge die can be used to connect base die sections to form a functionally monolithic base die according to an embodiment.FIGS. 5A-5C illustrate a situation where a top layer interconnection structure is used and a situation where bridge die are used to connect base die sections according to an embodiment.FIG. 6A illustrates a wafer that includes a plurality of die according to an embodiment.FIG. 6B is a flowchart of a die harvesting process according to an embodiment.FIG. 6C illustrates die quadrants associated with a reticle according to an embodiment.FIG. 7 shows a flowchart of a method for providing high performance microprocessor die according to an embodiment.FIG. 8 illustrates a computing device in accordance with one implementation of an embodiment.FIG. 9 illustrates an interposer that includes one or more implementations of an embodiment. It is noted that only figures 6B and 6C show embodiments which are in accordance with the claimed invention. The other figures show embodiments which do not form part of the claimed invention but are useful for understanding it. DESCRIPTION OF THE EMBODIMENTS A die interconnection scheme for providing a high yielding process for high performance microprocessors is described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be