Search

EP-3678292-B1 - MAGNETICALLY PUMPED VOLTAGE CONTROLLED OSCILLATOR

EP3678292B1EP 3678292 B1EP3678292 B1EP 3678292B1EP-3678292-B1

Inventors

  • HSUEH, YU-LI
  • HUANG, PO-CHUN
  • LIN, ANG-SHENG
  • CHIU, WEI-HAO

Dates

Publication Date
20260506
Application Date
20191120

Claims (5)

  1. A voltage controlled oscillator (300, 400) comprising: a first inductor (L1), having a first end (N11) and a second end (N12); a second inductor (L2), having a first end (N21) and a second end (N22), wherein the first end (N21) of the second inductor (L2) is electrically coupled to the first end (N11) of the first inductor (L1); a first P-channel metal oxide semiconductor, PMOS, transistor (MP1), having a gate node, a drain node, and a source node, wherein the drain node of the first PMOS transistor (MP1) is electrically coupled to the second end (N12) of the first inductor (L1), and the source node of the first PMOS transistor (MP1) is electrically coupled to a first power rail; a second PMOS transistor (MP2), having a gate node, a drain node, and a source node, wherein the drain node of the second PMOS transistor (MP2) is electrically coupled to the second end (N22) of the second inductor (L2), and the source node of the second PMOS transistor (MP2) is electrically coupled to the first power rail; a first N-channel metal oxide semiconductor, NMOS, transistor (MN1), having a gate node, a drain node, and a source node, wherein the drain node of the first NMOS transistor (MN1) is electrically coupled to the second end (N12) of the first inductor (L1), and the source node of the first NMOS transistor (MN1) is electrically coupled to a second power rail; a second NMOS transistor (MN2), having a gate node, a drain node, and a source node, wherein the drain node of the second NMOS transistor (MN2) is electrically coupled to the second end (N22) of the second inductor (L2), and the source node of the second NMOS transistor (MN2) is electrically coupled to the second power rail; and an inductor-capacitor, LC, tank circuit (302, 402), electrically coupled to the gate node of the first PMOS transistor (MP1), the gate node of the second PMOS transistor (MP2), the gate node of the first NMOS transistor (MN1), and the gate node of the second NMOS transistor (MN2), wherein energy is magnetically pumped into the LC tank circuit (302, 402) through the first inductor (L1) and the second inductor (L2), such that there is no direct connection between the LC tank circuit (302, 402) and the drain node of each of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) and there is no direct connection between the LC tank circuit (302, 402) and the drain node of each of the second PMOS transistor (MP2) and the second NMOS transistor (MN2), and wherein the LC tank circuit (302, 402) comprises a capacitor, wherein the capacitor is a voltage-controlled capacitor that is usable to adjust a resonant frequency of the LC tank circuit (302, 402) in response to a control voltage; wherein a first end of the capacitor is coupled to the gate node of the second PMOS transistor (MP2) and the gate node of the second NMOS transistor (MN2), and a second end of the capacitor is coupled to the gate node of the first PMOS transistor (MP1) and the gate node of the first NMOS transistor (MN1); a third inductor (L3), magnetically coupled to the first inductor (L1), wherein a first end (N31) of the third inductor (L3) is electrically coupled to a first bias voltage, and a second end (N32) of the third inductor (L3) is electrically coupled to the first end (N51) of the capacitor; and a fourth inductor (L4), magnetically coupled to the second inductor (L2), wherein a first end (N41) of the fourth inductor (L4) is electrically coupled to the first bias voltage, and a second end (N42) of the fourth inductor (L4) is electrically coupled to the second end (N52) of the capacitor.
  2. The voltage controlled oscillator (300, 400) of claim 1, wherein the first end (N11) of the first inductor (L1) and the first end (N21) of the second inductor (L2) are electrically coupled to the first bias voltage; or wherein the first end (N11) of the first inductor (L1) and the first end (N21) of the second inductor (L2) are electrically coupled to a second bias voltage, and a setting of the first bias voltage is independent of a setting of the second bias voltage.
  3. A voltage controlled oscillator (500) comprising: a first inductor (L1), having a first end (N11) and a second end (N12); a second inductor (L2), having a first end (N21) and a second end (N22), wherein the first end (N21) of the second inductor (L2) is electrically coupled to the first end (N11) of the first inductor (L1); a third inductor (L3), having a first end (N31) and a second end (N32); a fourth inductor (L4), having a first end (N41) and a second end (N42), wherein the first end (N41) of the fourth inductor (L4) is electrically coupled to the first end (N31) of the third inductor (L3); a first P-channel metal oxide semiconductor, PMOS, transistor (MP1), having a gate node, a drain node, and a source node, wherein the drain node of the first PMOS transistor (MP1) is electrically coupled to the second end (N12) of the first inductor (L1), and the source node of the first PMOS transistor (MP1) is electrically coupled to a first power rail; a second PMOS transistor (MP2), having a gate node, a drain node, and a source node, wherein the drain node of the second PMOS transistor (MP2) is electrically coupled to the second end (N22) of the second inductor (L2), and the source node of the second PMOS transistor (MP2) is electrically coupled to the first power rail; a first N-channel metal oxide semiconductor, NMOS, transistor (MN1), having a gate node, a drain node, and a source node, wherein the drain node of the first NMOS transistor (MN1) is electrically coupled to the second end (N32) of the third inductor (L3), and the source node of the first NMOS transistor (MN1) is electrically coupled to a second power rail; a second NMOS transistor (MN2), having a gate node, a drain node, and a source node, wherein the drain node of the second NMOS transistor (MN2) is electrically coupled to the second end (N42) of the fourth inductor (L4), and the source node of the second NMOS transistor (MN2) is electrically coupled to the second power rail; and an inductor-capacitor, LC, tank circuit (502), electrically coupled to the gate node of the first PMOS transistor (MP1), the gate node of the second PMOS transistor (MP2), the gate node of the first NMOS transistor (MN1), and the gate node of the second NMOS transistor (MN2), wherein energy is magnetically pumped into the LC tank circuit (502) through the first inductor (L1), the second inductor (L2), the third inductor (L3), and the fourth inductor (L4), such that there is no direct connection between the LC tank circuit (502) and the drain node of each of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) and there is no direct connection between the LC tank circuit (502) and the drain node of each of the second PMOS transistor (MP2) and the second NMOS transistor (MN2); wherein the LC tank circuit (502) comprises: a capacitor, wherein the capacitor is a voltage-controlled capacitor that is usable to adjust a resonant frequency of the LC tank circuit (502) in response to a control voltage, and wherein a first end (N51) of the capacitor is electrically coupled to the gate node of the second PMOS transistor (MP2) and the gate node of the second NMOS transistor (MN2), and a second end (N52) of the capacitor is electrically coupled to the gate node of the first PMOS transistor (MP1) and the gate node of the first NMOS transistor (MN1); a fifth inductor (L5), magnetically coupled to both of the first inductor (L1) and the third inductor (L3), wherein a first end (N31) of the third inductor (L3) is electrically coupled to a bias voltage, and a second end (N32) of the third inductor (L3) is electrically coupled to the first end (N51) of the capacitor; and a sixth inductor (L6), magnetically coupled to both of the second inductor (L2) and the fourth inductor (L4), wherein a first end (N41) of the fourth inductor (L4) is electrically coupled to the bias voltage, and a second end (N42) of the fourth inductor (L4) is electrically coupled to the second end (N52) of the capacitor.
  4. The voltage controlled oscillator (500) of claim 3, wherein the first end (N11) of the first inductor (L1) and the first end (N21) of the second inductor (L2) are electrically coupled to the second power rail.
  5. The voltage controlled oscillator (500) of claim 3, wherein the first end (N31) of the third inductor (L3) and the first end (N41) of the fourth inductor (L4) are electrically coupled to the first power rail.

Description

This application claims the benefit of U.S. provisional application No. 62/787,447, filed on 01/02/2019. Background The present invention relates to an oscillator circuit, and more particularly, to a magnetically pumped voltage controlled oscillator. In general, a voltage controlled oscillator (VCO) is an oscillator circuit that outputs an oscillating signal having a frequency that varies in response to an input control voltage. VCOs are fundamental components that are employed in a broad range of applications. By way of example, VCOs are utilized for phase locked loop (PLL) circuits. A conventional VCO may employ an inductor-capacitor (LC) tank to act as a resonator. The conventional VCO, however, has certain disadvantages resulting from direct connection between the LC tank and drain nodes of metal oxide semiconductor (MOS) transistors. WO 2013/063610 A1 describes an integrated circuit. WO 2017/075597 A1 describes examples of a voltage controlled oscillator for providing an oscillating output signal. US 2010/194485 A1 describes techniques for providing voltage-controlled oscillator circuits having improved phase noise performance and lower power consumption. US 2016/056762 A1 describes a split transformer based LC-tank oscillator. US 2014/077890 A1 describes a class-F CMOS oscillator. WO 2009/041868 A1 describes a Hartley voltage controlled oscillator. Summary One of the objectives of the claimed invention is to provide a magnetically pumped voltage controlled oscillator. The present invention is defined by the appended claims. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. Brief Description of the Drawings FIG. 1 is a circuit diagram illustrating a first magnetically pumped voltage controlled oscillator not according to the present invention.FIG. 2 is a circuit diagram illustrating a second magnetically pumped voltage controlled oscillator not according to the present invention.FIG. 3 is a circuit diagram illustrating a third magnetically pumped voltage controlled oscillator according to an embodiment of the present invention.FIG. 4 is a circuit diagram illustrating a fourth magnetically pumped voltage controlled oscillator according to an embodiment of the present invention.FIG. 5 is a circuit diagram illustrating a fifth magnetically pumped voltage controlled oscillator according to an embodiment of the present invention. Detailed Description Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to ...". Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. FIG. 1 is a circuit diagram illustrating a first magnetically pumped voltage controlled oscillator (VCO). The VCO 100 includes a single inductor-capacitor (LC) tank circuit 102, a plurality of inductors L1 and L2, and a plurality of N-channel metal oxide semiconductor (NMOS) transistors MN1 and MN2. The LC tank circuit 102 includes a plurality of inductors L3 and L4 and a capacitor C. By way of example, but not limitation, the capacitor C may be implemented by a voltage-controlled capacitor that is used to adjust a resonant frequency of the LC tank circuit 102 in response to a control voltage of the VCO. One end N11 of the inductor L1 is coupled to a power rail VDD, and the other end N12 of the inductor L1 is coupled to a drain node of the NMOS transistor MN1. One end N21 of the inductor L2 is coupled to the power rail VDD, and the other end N22 of the inductor L2 is coupled to a drain node of the NMOS transistor MN2. A source node of the NMOS transistor MN1 and a source node of the NMOS transistor MN2 are both coupled to a power rail GND. The power rail VDD is used to deliver a supply voltage (e.g., 0.6V or 0.8V), and the power rail GND is used to deliver a ground voltage (e.g., 0V). The LC tank circuit 102 is coupled to a gate node of the NMOS transistor MN1 and a gate node of the NMOS transistor MN2. Energy is magnetically pumped into the LC tank circuit 102 through the inductors L1 and L2, such that there is no direct connection between the LC tank circuit 102 and the drain node of the MOS transistor MN1 and there is no direct connection between th