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EP-3686890-B1 - APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUBBLOCKS OF MEMORY CELLS

EP3686890B1EP 3686890 B1EP3686890 B1EP 3686890B1EP-3686890-B1

Inventors

  • TANZAWA, TORU

Dates

Publication Date
20260513
Application Date
20130820

Claims (12)

  1. A stacked memory structure, comprising: a stack including multiple arrays (102, 302, 304, 306, 308) of memory cells, the stack of multiple arrays of memory cells including multiple blocks of memory cells, each of the stacked arrays having multiple sub-blocks (320, 322, 324, 326, 340, 342, 344, 346, 360, 362, 364, 366, 380, 382, 384, 386) of memory cells arranged in rows and columns, wherein the multiple sub-blocks of memory cells are each part of respective blocks of memory cells, wherein only memory cells within a block can be enabled for access at the same time; one or more decoder circuits (200) configured to enable access to multiple selected sub-blocks of memory cells in a block of memory cells at the same time, wherein the enabled sub-blocks of memory cells includes multiple sub-blocks in each of multiple arrays (302, 304, 306, 308); wherein simultaneously enabled sub-blocks in a first array of the multiple arrays of memory cells are in different rows and columns from one another in the first array; and wherein simultaneously enabled sub-blocks in a second array of multiple array of memory cells are in different rows and columns from one another in the second array.
  2. The stacked memory structure of claim 1, wherein the simultaneously accessed sub-blocks in the first array are each in positions in the rows and columns in the first array which correspond to the positions of the simultaneously accessed sub-blocks in the second array in the rows and columns of the second array (320, 322, 324, 326, 340, 342, 344, 346, 360, 362, 364, 366, 380, 382, 384, 386).
  3. The stacked memory structure of claim 1, wherein the simultaneously accessed sub-blocks in the first array are each in different positions in rows and columns in the first array than the positions in rows and columns of the simultaneously accessed sub-blocks in the second array (421, 423, 427, 429, 441, 443, 445, 447, 461, 463, 467, 469, 481, 483, 485, 487).
  4. The stacked memory structure of claim 1, wherein the simultaneously accessed sub-blocks in the first array are directly over or under corresponding simultaneously accessed sub-blocks of the second array.
  5. A method of operating the stacked memory structure of any of the preceeding claims, the method comprising: simultaneously accessing first and second sub-blocks of memory cells within a first block of memory cells within the first array of memory cells including multiple blocks of memory cells, the first block including multiple sub-blocks in multiple rows and multiple columns within the first block; and accessing a third sub-block of memory cells within the first block of memory cells, the third sub-block located in the second array of memory cells including multiple sub-blocks of memory cells, simultaneously with accessing the first and second sub-blocks of the first array, wherein the first and second sub-blocks are in different rows of the first block and in different columns of the first block.
  6. The method of claim 5, wherein the memory cells in a second block of memory cells are not enabled to be accessed when memory cells of the first block are being accessed.
  7. The method of claim 5, when the first and second sub-blocks within the first block are enabled to be accessed, other sub-blocks within the first block are disabled for access.
  8. The method of claim 5, wherein the first array of memory cells and the second array of memory cells are arrays of NAND memory cells.
  9. The method of claim 5, wherein the first array of memory cells and the second array of memory cells are arrays of dynamic random access memory cells.
  10. The method of claim 5, wherein the first array of memory cells and the second array of memory cells are arrays of phase change memory cells.
  11. The method of claim 5, wherein the second array is over or under the first array.
  12. The method of claim 5, further comprising simultaneously accessing additional sub-blocks of the first block of memory cells with the first and second sub-blocks, wherein the multiple simultaneously accessed sub-blocks are in separate rows of sub-blocks of the first block of memory cells, and are in separate columns of sub-blocks of the first block of memory cells.

Description

BACKGROUND Semiconductor memory devices formed in integrated circuits (ICs) are used in many electronic devices such as personal digital assistants (PDAs), laptop computers, mobile phones and digital cameras. US2011/026303 discloses a non-volatile memory device comprising a plurality of independently operable memory banks, each including a plurality of resistance memory cells within a plurality of sub-blocks. During a test operation, data can be written within the plurality of sub-blocks simultaneously. SUMMARY The invention is defined in independent claims 1 and 5. Further preferred embodiments are defined in the dependent claims. Only embodiments of the description comprising all the technical features of the claims fall under the scope of protection of the claims while the remaining ones correspond to illustrative examples which are useful for the understanding of the relevant technical context. BRIEF DESCRIPTION OF THE DRAWINGS Some embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which: FIG. 1 is a block diagram of an apparatus in the form of a memory device according to various embodiments of the invention;FIG. 2 is a schematic circuit view of an apparatus in the form of a decoder circuit according to various embodiments of the invention;FIG. 3 is a block diagram of an apparatus in the form of a memory device according to various embodiments of the invention;FIG. 4 is a block diagram of the memory device of FIG. 3 according to various embodiments of the invention;FIG. 5 is a cross-sectional view of a semiconductor construction according to various embodiments of the invention;FIG. 6 is a flow diagram of one method according to various embodiments of the invention; andFIG. 7 is a block diagram of an apparatus in the form of a memory device according to various embodiments of the invention. DETAILED DESCRIPTION Aspects of the present disclosure comprise subject matter in accordance with the claims appended hereto. For the purposes of this document, a memory cell (cell) includes a phase change memory cell, a dynamic random access memory (DRAM) memory cell, or a charge storage memory cell, such as a transistor having a charge trap or a floating gate, for example, although embodiments are not specifically limited to just those cells. Each cell may comprise a multi-state device capable of storing one of multiple separate and distinct states, each state representing different data. An "apparatus" can refer to any of a number of structures, such as circuitry, a device or a system. Electrical current can flow in a cell during an operation such as a programming operation, a read operation or an erase operation on the cell. A substantial amount of current can flow through one region of a memory array if multiple cells are being accessed at the same time and the cells are near each other in the same region. The cells outside the region may not be drawing current when the cells in the region are being accessed, and an imbalance in current flow can result in noise in the memory array. The inventor has discovered that the challenges noted above, as well as others, can be addressed by accessing multiple sub-blocks of cells that are distributed across a memory array at the same time. The current that flows through the cells in the sub-blocks during an operation is then distributed across the memory array. FIG. 1 is a block diagram of an apparatus in the form of a memory device 100 according to various embodiments of the invention. A substantially rectangular two-dimensional array 102 of cells and a sense/cache circuit 104 are formed on a semiconductor substrate 106. The cells in the array 102 are divided into sub-blocks 110, 114, 116, 118, 120, 124, 126, 128, 130, 134, 136, 138, 140, 144, 146 and 148. Each of the sub-blocks 110-148 includes two or more cells that can be accessed by one or more access lines (e.g., word lines, not shown) and provide data on one or more data lines (not shown) that are coupled to the sense/cache circuit 104. For example, the sub-block 110 includes a cell 149. Each of the sub-blocks 110-148 may contain thousands of cells. A three-dimensional array of cells may comprise multiple two-dimensional arrays of cells such as the array 102 stacked one over the other. The illustrated array 102 is divided into four rows of sub-blocks, each row of sub-blocks in the array 102 comprising a sub-array including four of the sub-blocks 110-148. The illustrated array 102 is also divided into four columns of the sub-blocks 110-148. Boundaries of the sub-blocks 110-148 are shown by horizontal and vertical lines in FIG. 1. Each of the sub-blocks 110-148 in the array 102 has a location that can be defined with reference to a first coordinate and a second coordinate in a coordinate system. For example, each sub-block can be located in a two-dimensional array with reference to an x-coordinate and a y-coordinate from a reference location (e.g., origin)