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EP-3729495-B1 - INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS

EP3729495B1EP 3729495 B1EP3729495 B1EP 3729495B1EP-3729495-B1

Inventors

  • LAJOIE, Travis
  • WANG, PEI-HUA
  • KU, CHIEH-JEN
  • SHARMA, ABHISHEK A.
  • GHANI, TAHIR
  • KAVALIEROS, JACK T.
  • OGADHOH, SHEM O.
  • WANG, YIH
  • SELL, BERNHARD
  • GARDINER, Allen
  • LIN, BLAKE
  • ALZATE VINASCO, Juan G.

Dates

Publication Date
20260513
Application Date
20171222

Claims (7)

  1. A semiconductor device (100), comprising: a transistor (120) having a source area (111) and a drain area (113) within a substrate (101), and a gate electrode (115) above the substrate (101); an interconnect structure (110) above the substrate (101), wherein the interconnect structure (110) includes: an inter-level dielectric (ILD) layer (105); a further inter-level dielectric ILD layer (103) above the substrate 101 and below the ILD layer (105); a separation layer (106) above the ILD layer (105); a further separation layer (104) between the ILD layer (105) and the further ILD layer (103); a first conductor within the ILD layer (105), wherein the first conductor has a first physical configuration; and a second conductor within the ILD layer (105), wherein the second conductor has a second physical configuration different from the first physical configuration; interstitial bridge via within the ILD layer (105), and the first conductor is coupled to the second conductor through the interstitial bridge via in a lateral direction parallel or vertical direction perpendicular to a surface of the ILD layer (105) or the first conductor directly overlaps with the second conductor, wherein the further separation layer (104) includes a barrier layer comprising a material layer that is capable of reducing or preventing metallic ions of the first conductor and the second conductor from diffusing into the surrounding regions of the substrate (101).
  2. The semiconductor device (100) of claim 1, wherein the first physical configuration of the first conductor includes a shape, a size, a height, or a material of the first conductor, a first depth from a first surface of the ILD layer (105) to the first conductor, or a second depth from a second surface of the ILD layer (105) to the first conductor.
  3. The semiconductor device (100) of any one of claims 1 or 2, wherein the first conductor or the second conductor includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.
  4. The semiconductor device (100) of any one of claims 1, 2 or 3, wherein the first conductor or the second conductor has a triangular shape, a square shape, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.
  5. The semiconductor device (100) of any one of claims 1, 2, 3 or 4, wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.
  6. The semiconductor device (100) of any one of claims 1, 2, 3, 4 or 5, wherein the ILD layer (105) includes silicon dioxide (SiO 2 ), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, or organosilicate glass.
  7. The semiconductor device (100) of any one of claims 1, 2, 3, 4, 5 or 6, wherein the separation layer (106) includes one or more of an etching stop layer, a barrier layer, a capping layer, or a hard mask layer.

Description

Field Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to interconnect structures for integrated circuits. Background Interconnect structures for an integrated circuit (IC) or a semiconductor device, e.g., a memory, a logic application, a radio frequency (RF) application, may connect various components of the IC or the semiconductor device to function together. An interconnect structure may include multiple layers of conductors coupled to each other by vias through inter-level dielectric (ILD) layers separating the conductors. A conductor may also be referred to as a conductive contact, a contact, a metal line, or any other terms used in the industry. Vias may be used to connect one conductor in a metal layer to another conductor in another metal layer. An interconnect structure may include multiple conductors formed as multiple metal lines patterned and etched in multiple steps. More routing and extra process steps may be performed at upper metal layers to connect the conductors at the upper metal layers than for conductors at the lower metal layers. Fabrication of interconnect structures may be among the most process-intensive and cost-sensitive portions of IC manufacturing. US 2008/105977 A1 discloses a structure including an interlevel dielectric layer, a first electrically conductive line and a second electrically conductive line. The structure further includes a diffusion barrier region residing in the interlevel dielectric layer. US 9 786 557 B1 discloses a structure comprising an interlayer dielectric formed on top of a shallow trench isolation area. The interlayer dielectric comprises openings for gates which are formed on a substrate. Further, source and drains are formed below the interlayer dielectric. US 2005/079669 A1 discloses a structure comprising a conductor formed on a support layer 10. On top of the supper layer and the conductor is a first dielectric layer formed. Further, the dielectric comprises a via hole and a recess. An intermediate layer formed above the support layer separates dielectric layer from a layer comprising tungsten. The layer comprising tungsten forms a first electrode and a via hole conductor. US 2017/343498 A1 discloses a biosensor. The biosensor comprises a heater, which is a part of a back-end-of-line interconnect structure. The interconnect structure is arranged above a carrier substrate. Further a semiconductor substrate is arranged above the interconnect structure. The semiconductor substrate accommodates a BioFET, which is arranged at an underside of the semiconductor substrate. The interconnect structure may comprise an upper interlayer dielectric US 2017/263715 A1 discloses a device comprising a dielectric layer above a gate electrode structure formed in a dielectric material layer. A sacrificial organic mix layer is formed on top of the dielectric material layer to form patterns through the sacrificial organic mix layer into the dielectric layer for M0, CB and CA to TS formations. After removing the sacrificial layer a metal layer is formed on top of the dielectric forming the M0, CB and CA to TS formations in the patterns in the dielectric layer. US 2017/084531 A1 discloses an integrated circuit that includes a first semiconductor device and a second semiconductor device formed using a bulk silicon wafer and disposed on a glass substrate. The first/second semiconductor device has a source region and has a drain region. The source region and the drain region are formed in a first/second semiconductive region. A gate of the first/second semiconductor device may be disposed between the glass substrate and the first/second semiconductive region. Further, the integrated circuit comprises an interlayer dielectric material, which may electrically isolate the first semiconductive region from the second semiconductive region. US 2016/141291 A1 discloses an integrated circuit device comprising a plurality of metal segments. The plurality of metal segments of a M0 layer may be utilized to provide local interconnections between two or more CB contacts through and/or two or more CA contacts in the integrated circuit device. In addition, an interconnecting M0 metal segment may also provide a landing pad for a via that may be connected to another metal layer. US2007/0077722 discloses a flat type capacitor for an integrated circuit and a method of manufacturing the same. Metal interconnections are formed in a plurality of interlayer dielectric (ILD) layers. Brief Description of the Drawings Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. Figure 1 schematically illustrates a diagram of an interconnect structure of a semiconduc