EP-3734585-B1 - DISPLAY PANEL AND DISPLAY DEVICE

Inventors

• LI, WENYING

Dates

Publication Date

20260513

Application Date

20180112

Claims (3)

1. A display panel, comprising: an array substrate and a color film substrate, wherein the array substrate is provided with a plurality of data lines (D1, ..., Dh), a plurality of gate line sets (G1, ..., Gn) arranged in parallel to each other, a plurality of first thin film transistors (T1), a plurality of second thin film transistors (T2), a pixel electrode and a first common electrode (COM1), a second common electrode (COM2) disposed on the color filter substrate, wherein the pixel electrode and the second common electrode (COM2) form a liquid crystal capacitor; each set of the gate line sets (G1, ..., Gn) comprises a first gate line (g1,..., gn) and a second gate line (g1', ..., gn'), wherein the first gate line (g1, ..., gn) and the second gate line (g1', ..., gn') are arranged in parallel to each other; the second thin film transistors (T2) are disposed at intersecting points of the second gate lines (g1', ..., gn') and the data lines (D1, ..., Dh); gate electrodes of the second thin film transistors (T2) are connected to the second gate lines (g1', ..., gn') correspondingly, source electrode of the second thin film transistors (T2) are connected to the data lines (D1, ..., Dh) correspondingly, and drain electrodes of the second thin film transistors (T2) are connected to the pixel electrode; wherein gate electrodes of the first thin film transistors (T1) are connected to the first gate lines (g1, ... , gn) correspondingly, source electrodes of the first thin film transistors (T1) are connected to the second gate lines (g1', ..., gn') correspondingly, and the first common electrode (COM1) is connected to the drain electrodes of the first thin film transistors (T1), and each of the first gate lines (g1, ... , gn) and the second gate lines (g1', ..., gn') is connected to at least two of the first thin film transistors (T1); wherein the display panel further comprises a gate driver; wherein the display panel is characterized in that : the gate driver is disposed on two sides of the display panel so that the display panel drives both sides of the display panel through the gate driver, wherein the sources of the at least two of the first thin film transistors (T1) are connected to a middle section of each of the second gate lines (g1', ..., gn'); and each of the second gate lines (g1', ..., gn') corresponds to one of the first gate lines (g1, ..., gn), and a ratio of a number of the first thin film transistors (T1) connecting the first gate lines (g1, ..., gn) to a number of the second thin film transistors (T2) connecting the corresponding second gate lines (g1', . ., gn') ranges from 1/5 to1/10; the gate driver is adapted to control the first gate lines and the second gate lines such that: the second gate line (g1', ..., gn') of an i-th gate line set (G1, ..., Gn) inputs a turn-on signal of high voltage level during a duration 2t, and at the same time, a signal is not input to the first gate line (g1, ..., gn) of the i-th gate line set (G1, ..., Gn), such that the second thin film transistor (T2) is turned on, and the first thin film transistor (T1) is turned off,then the second gate line (g1', ..., gn') of the i-th gate line set (G1, ..., Gn) inputs a turn-off signal of low voltage level, and at the same time, the turn-on signal of high voltage level is input to the first gate line (g1, ..., gn) of the i-th gate line set (G1, ..., Gn) during a duration t, so that the second thin film transistor (T2) is turned off and the first thin film transistor (T1) is turned on, such that the first thin film transistor (T1) is used to accelerate a speed of turning off the second thin film transistor (T2); wherein the number of the i-th is an integer.
2. The display panel according to claim 1, characterized in that the first common electrode (COM1) voltage is less than or equal to a turned off voltage of the first thin film transistor (T1).
3. A display device, characterized in comprising: the display panel according to claim 1 or 2.

Description

FIELD OF DISCLOSURE The disclosure relates to the field of displaying techniques, and in particular to a display panel and a display device. BACKGROUND OF DISCLOSURE Due to development of liquid crystal display (LCD) technology, more and more users are using LCD devices. Size of LCD panels is getting larger and larger, and resolution of the LCD panels is also getting higher and higher. The LCD panels usually provide a turn-on voltage for a thin-film transistor (TFT) through a gate driver, and the LCD panels provide a data signal for the TFT through a source driver. When the TFT is under control of the gate driver and is turned on, at the same time, a source driver charges a subpixel. Referring to FIG. 1, a relation view shows between a charging time and a resolution of a known pixel. As shown in FIG. 1, because resolution Res of the LCD panel is greatly increased, charging time of the pixel is shortened. For example, a panel with FHD resolution is driven at 120HZ by a gate driver, at which time a gate line charges approximately 7.4us. In addition, for a panel having 4K2K resolution, because the number of gate lines is increased from 1080 to 2160 and driven by the gate driver at 120HZ, at which time the charging time of one gate line is reduced by about half to 3.7us. If the RC load in the pixel cannot be made smaller, scanning speed of the gate line will be slower, which will affect display of the liquid crystal display panel. U.S. patent application No. 2002/011982 A1 to Masanori Takeuchi et al., entitled: "image display device", discloses an image display device. The image display device according is an active-matrix display device which has a plurality of scanning lines and a plurality of signal lines respectively disposed in directions to mutually intersect, and a plurality of display pixels disposed in a matrix, each of which is connected via a pixel switching element to each intersecting point where the lines intersect. The image display device includes scanning auxiliary lines which are respectively provided to the scanning lines. In the image display device, each of the discharging TFTs in one scanning line is connected to all the gate electrodes of the pixels TFT in the same scanning line. Therefore, a problem of the driving signal being slowly released at a middle section of a gate line or a position far away from a gate driver can appear. Furthermore, a turned-on time of the discharging TFT is same as a turned-on time of the pixels TFT, so the discharging TFT and the pixels TFT cannot be controlled independently. U.S. patent application No. 2004/041153 A1 to Ju-Young Lee, entitled: "array substrate for liquid crystal display device", discloses an array substrate for use in a liquid crystal display including a transparent substrate; a plurality of gate lines arranged over the transparent substrate in a transverse direction; a plurality of data lines arranged over the transparent substrate in a longitudinal direction substantially perpendicular to the plurality of gate lines, intersections of the plurality of data lines and the plurality of gate lines defining a plurality of pixel regions; a gate driver contacting ends of the plurality of gate lines and sequentially scanning a gate pulse to the plurality of gate lines; a data driver contacting ends of the plurality of data lines and applying a data pulse to the plurality of data lines; a plurality of pixel electrodes disposed in the plurality of pixel regions; a plurality of first thin-film transistors disposed in the plurality of pixel regions, each first thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel region; a feed line outputting an OFF voltage to the plurality of first thin-film transistors; and a plurality of second thin-film transistors contacting each other and connecting the feed line to the plurality of gate lines. In the array substrate, the gate electrodes of the thin-film transistors are respectfully connected to gate lines, and one of the thin-film transistors is connected to all gate electrodes of in one same gate line. Therefore, the aforesaid problem of uneven discharging time of the thin film transistors and unable to control transistors independently cannot be solved either. U.S. patent application No. 2014/092082 A1 entitled: "liquid crystal display device", discloses an LCD device. The LCD device includes a liquid crystal display panel in which n gate lines are formed; a timing controller to generate first to sixth clock signals; a first gate driver to apply a high gate voltage to one ends of the (2k-1)th gate lines in response to the first, third and fifth clock signals; a second gate driver to apply the high gate voltage to one ends of the (2k)th gate lines in response to the second, fourth and sixth clock signals; left discharge circuits each to apply a low gate voltage to the other end of the (2k-1)th gate lin