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EP-3761511-B1 - FREQUENCY MULTIPLIER, DIGITAL PHASE LOCK LOOP CIRCUIT AND FREQUENCY MULTIPLYING METHOD

EP3761511B1EP 3761511 B1EP3761511 B1EP 3761511B1EP-3761511-B1

Inventors

  • GAO, PENG

Dates

Publication Date
20260506
Application Date
20190329

Claims (8)

  1. A system comprising: a frequency multiplier (401), applied to a digital phase-locked loop circuit, the frequency multiplier (401) having a first input, a second input and an output; a time-to-digital converter (402) having a first input, a second input and an output; a digital loop filter (403) having an input and an output; a digital controlled oscillator (404) having an input and an output; a frequency divider (405) having an input and an output; wherein the first input of the time-to-digital converter (402) is coupled to the output of the frequency divider (405), and the second input of the time-to-digital converter (402) is coupled to the output of the frequency multiplier (401), and the output of the time-to-digital converter (402) is coupled to both the input of the digital loop filter (403) and the second input of the frequency multiplier (401); the output of the digital loop filter (403) is coupled to the input of the digital controlled oscillator (404); the input of the frequency divider (405) is coupled to the output of the digital controlled oscillator (404) configured to output an oscillation signal from the system; and the first input of the frequency multiplier (401) is coupled to a reference clock, wherein the frequency multiplier (401) comprises: a clock calibration circuit (502) having a first input, a second input and an output; a clock controller (501) having an input and an output; a clock frequency multiplier (503) having an input and an output; wherein the first input of the clock calibration circuit (502) is coupled to the reference clock, the second input of the clock calibration circuit (502) is coupled to the output of the clock controller (501), and the output of the clock calibration circuit (502) is coupled to the input of the clock frequency multiplier (503); the input of the clock controller (501) is coupled to the output of the time-to-digital converter (402); and the output of the clock frequency multiplier (401) is coupled to the second input of the time-to-digital converter (402), wherein the clock frequency multiplier (503) comprises: a clock delay circuit (5031) having an input and an output, an XOR gate circuit (5032) having a first input, a second input and an output; wherein the input of the clock delay circuit (5031) is coupled to the output of the clock calibration circuit (502), and the output of the clock delay circuit (5031) is coupled to the first input of the XOR gate circuit (5032); the second input of the XOR gate circuit (5032) is coupled to the output of the clock calibration circuit (502), and the output of the XOR gate circuit (5032) coupled to the second input of the time-to-digital converter (402), wherein the clock controller (501) is configured to receive an output signal of the time-to-digital converter (402) and generate a control signal based on a duty cycle error of the output signal; the clock calibration circuit (502) is configured to receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal; and the clock frequency multiplier (503) is configured to receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter (402), wherein the frequency multiplied signal is output after doubling the frequency of the received reference clock signal; wherein the clock controller (501) is specifically configured to determine the duty cycle error based on a difference between two adjacent discrete point signals of the output signal, and perform an integral operation on the duty cycle error to obtain the control signal, wherein the duty cycle error of the reference clock signal is equal to a difference between the duty cycle of the reference clock signal and a 50% duty cycle of the reference clock signal.
  2. The system according to claim 1, wherein the clock controller (501) comprises: a differentiator (701) having an input and output, a sampler (702) having an input and an output , and integrator (703) having an input and output; wherein the input of the differentiator (701) is coupled to the output of the time-to-digital converter (402); the input of the sampler (702) is coupled to the output of the differentiator (701); the input of the integrator (703) is coupled to the output of the sampler (702); and the output of the integrator (703) is coupled to the second input of the clock calibration circuit (502).
  3. The system according to claim 1, wherein the clock controller (501) comprises: a differentiator (801) having an input and output, an absolute value calculator (802) having an input and an output, and integrator having an input and output; wherein the input of the differentiator (801) is coupled to the output of the time-to-digital converter (402); the input of the absolute value calculator (802) is coupled to the output of the differentiator (801); the input of the integrator (803) is coupled to the output of the absolute value calculator (802) ; and the output of the integrator (803) is coupled to the second input of the clock calibration circuit (502).
  4. A frequency multiplication method, applied to the system of claims 1-3, the method comprising: receiving (1001) the output signal of the time-to-digital converter (402) in a digital phase-locked loop circuit, and generating a the control signal based on the duty cycle error of the output signal; and calibrating (1002) the duty cycle of the received reference clock signal based on the control signal to obtain the calibrated clock signal, multiplying the frequency of the calibrated clock signal, and outputting the frequency multiplied signal, wherein the generating a control signal based on the duty cycle error comprises: determining the duty cycle error based on a difference between two adjacent discrete point signals of the output signal, and performing an integral operation on the duty cycle error to obtain the control signal.
  5. The method according to claim 4, wherein the determining the duty cycle error based on a difference between two adjacent discrete point signals of the output signal comprises: using a difference between a value of a k th discrete point signal of the output signal and a value of a (k-1) th discrete point signal of the output signal as a value of the k th discrete point signal in the duty cycle error, to obtain the duty cycle error, wherein k is a natural number greater than or equal to 1.
  6. The method according to any one of claims 4 or 5, wherein the performing an integral operation on the duty cycle error to obtain the control signal comprises: sampling one discrete point signal every P discrete point signals in the duty cycle error to obtain a sampled signal, wherein P is equal to 2n and n is an integer greater than 0; and performing an integral operation on the sampled signal to obtain the control signal.
  7. The method according to any one of claims 4 or 5, wherein the performing an integral operation on the duty cycle error to obtain the control signal comprises: calculating and outputting an absolute value for a value of a k th discrete point signal in the duty cycle error, to obtain a duty cycle error after an absolute value operation, wherein k is a natural number greater than or equal to 1; and performing an integral operation on the duty cycle error obtained after the absolute value operation, to obtain the control signal.
  8. The method according to any one of claims 4 to 7, wherein the multiplying a frequency of the calibrated clock signal comprises: performing delay processing on the calibrated clock signal to obtain a delayed signal; and performing XOR processing on the calibrated clock signal and the delayed signal, to obtain a signal that is obtained after the frequency of the calibrated clock signal is multiplied.

Description

TECHNICAL FIELD This application relates to the field of communications technologies, and in particular, to a system comprising a frequency multiplier in a digital phase-locked loop circuit, and a frequency multiplication method. BACKGROUND A radio frequency transceiver widely uses a frequency synthesizer of a phase-locked loop (PLL) structure to generate a local oscillation signal (LO), to perform signal frequency conversion. Phase noises of the local oscillation signal directly affect quality of a communication signal, and affect a throughput. In the prior art, a frequency of a reference clock in a phase-locked loop is increased to improve phase noise performance of the phase-locked loop. Ideally, a timing relationship between a reference clock signal and a frequency multiplied signal that is obtained after frequency multiplication may be shown in FIG. 1. CLK_REF2X denotes the frequency multiplied signal that is obtained after frequency multiplication is performed on the reference clock signal CLK_REF. A frequency of the frequency multiplied signal is twice a frequency of the reference clock signal, but a cycle TREF2X of CLK_REF2X is only half of a cycle TREF of CLK_REF. However, quality of an output signal in a clock frequency multiplier circuit in the prior art heavily relies on a duty cycle of an input reference clock signal. Two adjacent clock cycles of the output signal CLK_REF2X in the clock frequency multiplier circuit alternate when the duty cycle of the input reference clock signal is not 50%. For details, refer to FIG. 2. In FIG. 2, the two adjacent clock cycles of CLK_REF2X are TR2A and TR2B respectively, and TR2A is less than TR2B. Such an alternating clock cycle is equivalent to a result of introducing a high-frequency frequency modulation signal to the reference clock signal. Consequently, a spurious signal may occur in output signals in the phase-locked loop circuit. This compromises performance of a radio frequency communications system. Therefore, how to calibrate the duty cycle of the reference clock signal is an urgent problem to be resolved. US 2014/340132 A1 relates to a frequency synthesizing system, comprising a clock generator to generate a reference clock signal; a frequency doubler, including an input to receive the reference clock signal, to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal; a frequency multiplier, coupled to the frequency doubler, to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal; and a fractional-N synthesizer, coupled to the frequency multiplier, to generate an output clock signal in response to the frequency-multiplied clock signal. US 9 634 678 B1 relates to a feedback control system comprising: a controllable oscillator configured to generate an output clock signal based on at least one control signal generated using at least one error signal; and an error detector configured to generate the at least one error signal based on a rising edge difference between a rising edge of an input clock signal and a first corresponding edge of an edge alignment corrected feedback clock signal and further based on a falling edge difference between a falling edge of the input clock signal and a second corresponding edge of the edge alignment corrected feedback clock signal, wherein the edge alignment corrected feedback clock signal is at least partially based on the output clock signal SUMMARY The invention is set out in the appended claims. An example of this application provides a frequency multiplier, applied to a digital phase-locked loop circuit and including: a clock controller, configured to: receive an output signal of a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal; a clock calibration circuit, configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal; and a clock frequency multiplier, configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter. Because the output signal of the time-to-digital converter may indicate a difference between the duty cycle of the reference clock signal and an ideal duty cycle, a duty cycle error of the reference clock signal may be determined based on the output signal. In this way, the control signal generated based on the duty cycle error can be used to accurately calibrate the duty cycle of the reference clock signal, so that a calibrated duty cycle of the reference clock signal approaches the ideal duty cycle. In this way, the duty cycle of the reference clock signal is calibrated. In an optional implementation of this example, the clock controller furth