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EP-3762968-B1 - HIGH POWER SEMICONDUCTOR DEVICE WITH SELF-ALIGNED FIELD PLATE AND MESA TERMINATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

EP3762968B1EP 3762968 B1EP3762968 B1EP 3762968B1EP-3762968-B1

Inventors

  • KNOLL, LARS
  • MIHAILA, ANDREI
  • Kranz, Lukas

Dates

Publication Date
20260506
Application Date
20190305

Claims (10)

  1. A power semiconductor device comprising: a wide-bandgap semiconductor layer (1), the wide-bandgap semiconductor layer (1) having a first main side (2) and a second main side (3) opposite to the first main side (2), wherein the first main side (2) and the second main side (3) extend in a lateral direction and wherein the wide-bandgap semiconductor layer (1) comprises an active region (AR) and a termination region (TR), the termination region (TR) laterally surrounding the active region (AR), wherein the wide-bandgap semiconductor layer (1) has a first recess (9), which is recessed from the first main side (2) in the termination region (TR), the first recess (9) surrounding the active region (AR); a field plate (5) on the first main side (2) of the wide-bandgap semiconductor layer (1), the field plate (5) exposing a first portion of the wide-bandgap semiconductor layer (1) in the termination region (TR); a sidewall (9e) of the first recess (9) adjacent to the active region (AR) is laterally aligned with a circumferential edge (5e) of the field plate (5) such that in an orthogonal projection onto a plane parallel to the first main side (2) an edge of the recess defined by the upper end of the sidewall is within less than 1 µm from the circumferential edge of the field plate (5), characterized in that the wide-bandgap semiconductor layer (1) has a second recess (14) in the active region (AR) which is recessed from the first main side (2) of the wide-bandgap semiconductor layer (1), a depth of the second recess (14) is the same as a depth of the first recess (9), and the second recess (14) is filled with a filling material, wherein the filling material is an insulating material.
  2. A power semiconductor device according to claim 1, further comprising a dielectric layer (4) interposed between the field plate (5) and the wide-bandgap semiconductor layer (1) to separate the field plate (5) from the wide-bandgap semiconductor layer (1).
  3. A power semiconductor device according to claim 2, wherein a thickness of the dielectric layer (4) perpendicular to the lateral direction decreases with increasing lateral distance from the first recess (9).
  4. A power semiconductor according to claim 2 or 3, wherein the dielectric layer (4) has a thickness adjacent to the first recess (9) which is in a range between 0.02 µm and 1 µm.
  5. A power semiconductor device according to any one of claims 1 to 4, wherein the field plate (5) comprises at least one of aluminum, nickel, tungsten, and chromium.
  6. A power semiconductor device according to any one of the claims 1 to 5, wherein a depth of the first recess (9) is at least 4 µm.
  7. A power semiconductor device according to any one of the claims 1 to 6, wherein the wide-bandgap semiconductor layer (1) comprises one of silicon carbide, gallium nitride and gallium oxide.
  8. A method for manufacturing a power semiconductor device comprising the following steps: providing a wide-bandgap semiconductor layer (1) having a first main side (2) and a second main side (3) opposite to the first main side (2), wherein the first and the second main side (3) extend in a lateral direction and wherein the wide-bandgap semiconductor layer (1) comprises an active region (AR) and a termination region (TR) laterally surrounding the active region (AR); forming a field plate (5) on the first main side (2) of the wide-bandgap semiconductor layer (1), the field plate (5) exposing a first portion of the first main side (2) of the wide-bandgap semiconductor layer (1) in the termination region (TR); and anisotropic etching of the wide-bandgap semiconductor layer (1) in areas where the field plate (5) exposes the first portion of the first main side (2) of the wide-bandgap semiconductor layer (1) in the termination region (TR) to form a first recess (9) in the wide-bandgap semiconductor layer (1) in the termination region (TR) wherein the first recess (9) surrounds the active region (AR) and the sidewall (9e) of the first recess (9) adjacent to the active region (AR) is laterally aligned with the circumferential edge (5e) of the field plate (5) such that in an orthogonal projection onto a plane parallel to the first main side (2) the edge of the recess defined by the upper end of the sidewall is within less than 1 µm from the circumferential edge of the field plate (5), wherein the step of forming the field plate (5) comprises: forming a dielectric layer (4) on the first main side (2) of the wide-bandgap semiconductor layer (1); forming a first metal layer (7) on the dielectric layer (4); and patterning the first metal layer (7) and the dielectric layer (4) to expose at least the first portion of the first main side (2) of the wide-bandgap semiconductor layer (1) in the termination region (TR) where the first recess (9) is to be formed in the step of anisotropic etching and, to expose a third portion of the first main side (2) of the wide-bandgap semiconductor layer (1) in the active region (AR), wherein a second recess (14) is formed in the exposed second portion of the active region (AR) in the step of anisotropic etching together with the first recess (9) using the patterned first metal layer (7) at least as a part of an etching mask, , and wherein the patterned first metal layer (7) in the termination region (TR) forms the field plate (5) in the power semiconductor device and wherein the second recess (14) is filled with a filling material, wherein the filling material is an insulating material.
  9. The method according to claim 8, wherein the dielectric layer (4) is patterned before the step of forming the first metal layer (7) to form an opening in the dielectric layer (4) that exposes at least a second portion of the first main side (2) of the wide-bandgap semiconductor layer (1) in the active region (AR).
  10. The method according to claim 9, wherein the first metal layer (7) is formed to be in direct contact with the first main side (2) of the wide-bandgap semiconductor layer (1) through the opening in the dielectric layer (4).

Description

FIELD OF THE INVENTION The present invention relates to a power semiconductor device and to a method for manufacturing the same. BACKGROUND OF THE INVENTION Wide-bandgap (WBG) semiconductor materials such as silicon carbide (SiC), gallium nitride, gallium oxide, boron nitride, aluminum nitride, zinc oxide, diamond etc. allow to make semiconductor devices more powerful and energy efficient than those made from conventional semiconductor materials. However, high power semiconductor devices based on wide-bandgap semiconductor materials require an efficient edge termination to avoid electric field crowding at the edge of the main contact resulting in breakdown of the device at a relatively low breakdown voltage VBR. Edge termination may be provided in various ways including floating field rings, junction termination extension (JTE), field plates, mesa structures or some combination of these techniques. Floating field rings are produced annularly around the active region of the semiconductor device. The generation of floating field rings can be easily integrated in the manufacturing process since the floating field rings can be formed simultaneously with a main junction in many power semiconductor devices. On the other hand, the design of a high performance floating field ring termination is very challenging given the high number of factors (e.g. ring spacing) affecting the most important trade-off between breakdown voltage and occupied wafer area. Junction termination extension (JTE) is based on the controlled addition of opposite charges by ion implantation into the surface of the semiconductor layer provided as the drift region. JTE techniques provide good termination efficiencies. However, ion implantation in wide-bandgap materials is more difficult than in conventional semiconductor materials. Moreover, the implantation steps require high temperature implantation facilities and an annealing oven especially designed for activation of such wide-bandgap materials, which makes the fabrication comparably costly. Also the quality of the semiconductor surface and therewith the device yield has been found to be degraded during the activation. Bearing in mind the technologically difficult and expensive processing, besides the processing cost reduction, an implantation free design would enable fabrication of wide-bandgap material based rectifiers in conventional silicon cleanrooms. The field plating technique provides relative simplicity in process requirements. It is based on a metal layer positioned upon a dielectric layer. The field plate modifies the surface potential at the edge of the main contact (active region). As a result the depletion zone is extended and thus the electrical field as well. The electric field crowding at the edge of the main contact is reduced and shifted towards the edge of the field plate. There however, due to the increasing electric field crowding, the risk of dielectric failure increases, thus limiting the achievable electrical breakdown voltage. In high power devices the problem of dielectric failure is more pronounced than in conventional silicon devices as the critical electric field crowding is almost one order of magnitude larger than in conventional silicon devices. Mesa structure edge termination is another edge termination technique with rather simple process requirements. The technique consists of taking away material and therefore electric charges at the circumferential edge of the main contact by mechanically removal or etching of the semiconductor layer. From the article "A new edge termination technique for SiC power devices" by Shuntao Hu et al., Solid State Eletronics 48 (2004) pp1861-1688, there is known an edge termination technique based on a metal structure overlapping a dielectric filled mesa structure formed in a SiC epilayer. Compared to traditional field plate technique without mesa structure, field crowding at the metal corner can be alleviated by this configuration. Nevertheless premature breakdown occurs before an ideal breakdown voltage is achieved. This is because field crowding is caused by the difference in dielectric constant between SiC layer and the dielectric layer. To alleviate this effect, it is further proposed in this article to add another dielectric layer on top of the dielectric filled mesa with additional metal field plate extension overlapping the mesa structure. With this modification, in simulation, 80 % of the ideal breakdown voltage is achieved. From US 2011/0101369 A1 it is known a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area with a mesa shape disposed at a peripheral area of the semiconductor power device, a field plate, and a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein. The edge of the field plate and the edge of the mesa are vertically aligned. From EP 2 927 962 A2