Search

EP-3782009-B1 - SYSTEM AND METHODS FOR CHANGING ADDRESSES OF ONE OR MORE COMPONENTS

EP3782009B1EP 3782009 B1EP3782009 B1EP 3782009B1EP-3782009-B1

Inventors

  • BUSH, Stephen, P.
  • RADEMACHER, TIMOTHY, JOHN

Dates

Publication Date
20260513
Application Date
20190416

Claims (10)

  1. A method of determining addresses for a plurality of components (150, 205, 210), comprising: receiving, from a master device (215), an address change request; in response to the received address change request, updating a pseudorandom number generator, PRNG, state based on a previous state thereof; and for each component (150, 205, 210), retrieving a set of bits from the PRNG state to form a candidate address for the component and determining a new component address for the component based on the candidate address such that new component addresses of the plurality of components are determined based on different sets of bits retrieved from the same PRNG state.
  2. The method of claim 1, wherein the retrieving the set of bits from the PRNG state for each component includes retrieving a set of successive bits from the PRNG state.
  3. The method of claim 1, wherein the determining the new component address for the component includes determining whether the candidate address is a valid address for assigning to the component.
  4. The method of claim 3, wherein the determining whether the candidate address is a valid address includes determining whether the candidate address is a reserved address.
  5. The method of claim 3: wherein the determining whether the candidate address is a valid address includes determining whether the candidate address is a default address; and/or wherein the determining whether the candidate address is a valid address includes determining whether the candidate address is an address that has been assigned to another component (150, 205, 210).
  6. The method of claim 3, further comprising assigning the candidate address as the new component address of the component upon determining that the candidate address is a valid address for assigning to the component; or further comprising updating the candidate address upon determining that the candidate address is not a valid address for assigning to the component.
  7. The method of any preceding claim, wherein the method is performed by each of the plurality of components (150, 205, 210) such that each of the plurality of components determines the same respective address for each of the plurality of components.
  8. A method of setting addresses of a plurality of components, comprising: sending, by a master device (215), a command to a security module (160) to retrieve new addresses for the plurality of components (150, 205, 210); in response to the received command, generating, by the security module (160), a plurality of new addresses for the plurality of components (150, 205, 210) based on a pseudorandom number generator, PRNG, state, and sending, by the security module, the plurality of new addresses to the master device (215); in response to receiving the plurality of new addresses from the security module (160), sending, by the master device (215), an address change request to each of the plurality of components (150, 205, 210); in response to the received address change request, generating, by each component (150, 205, 210), new addresses for the plurality of components based on the PRNG state, the new addresses generated by each component corresponding to the plurality of new addresses generated by the security module (160); and using, by each component (150, 205, 210), a distinct new address from the plurality of new addresses as a new component address determined based upon an index value associated with the component.
  9. The method of claim 8, wherein the generating the plurality of new addresses by the security module (160) and each component (150, 205, 210) includes retrieving, for each component, a set of bits from the PRNG state to form a candidate address for each component, and determining, for each component, a new address based on the candidate address.
  10. The method of claim 9, wherein the determining the new address for each component (150, 205, 210) includes determining whether the candidate address is one of a reserved address, a default address, and an address that has been assigned to another component.

Description

BACKGROUND 1. Technical Field The present disclosure generally relates to addressing schemes and, more particularly, to changing addresses of components in an imaging device to provide enhanced security. 2. Description of the Related Art Many computing systems, such as imaging systems, allow communication with peripheral devices using a shared bus to communicate data therebetween. Such a system is efficient in that a single bus is connected to each device. However, a set of rules or protocols is required in order to provide an orderly data flow so that more than one device does not attempt to use the shared bus at the same time. Often, a master or host device is the dominant device and controls the communications with the other devices, also known as slave devices. With this type of data communication system, the master device determines when to communicate with a slave device, and in response thereto, the slave device responds. The slave devices do not, on their own, initiate communications with the master device. One well-known protocol for orderly data communications between the master device and one or more slave devices is the Inter-Integrated Circuit (I2C) protocol. In the I2C protocol, each slave device is uniquely identified with an address. When the master device, also known as a bus master, initiates communications with a specific slave device, the address of the slave device is transmitted with data and/or a command on the shared bus during the initiation of the communication. While all of the slave devices connected to the shared bus receive the data and/or command and the address from the bus master, only the slave device with the matching address responds to the data and/or command and sends back an acknowledgment to the bus master. In some imaging devices, electronic authentication schemes associated with consumable supply items may be used. Consumable supply items may contain an integrated circuit chip or security device that communicates with a controller located in the imaging device. In such an arrangement, the imaging device includes a master device that initiates and controls passing of all communications including data, addresses, clock signals, and other control signals on a shared bus, and each supply item may be configured as a slave device. The master device may check the authenticity of each slave device by sending a verification challenge thereto and determining if the slave device correctly responds to the verification challenge. The authenticity is verified by the master device receiving from the slave device the correct response to the challenge. Otherwise, if the slave device does not respond correctly, the slave device may be detected as a clone or counterfeit and appropriate actions may be taken to protect against the use of unauthorized supply items in order to optimize performance of and/or prevent damage to the imaging device. Some security devices in supply items communicate with the imaging device using 10-bit addressing on an I2C bus and use address changing as a security feature. In some address changing schemes, a certain number of bits of the supply item address are fixed based on a given supply type while the remaining bits are variable with an initial value of zero. Upon receiving an address change command, the security device of the supply item may change the variable portion of the address to a new value. The bus master in the imaging device may then communicate with that supply item using the new address. Periodically changing the addresses of supply items provides enhanced security since it increases the difficulty for unauthorized components to communicate with the bus master. Support for 10-bit addressing mode, however, may not be as widespread with many I2C controllers supporting only 7-bit addressing. Unlike 10-bit addressing, 7-bit addressing generally results in higher data throughput because only one byte is required for an address compared to two bytes in 10-bit addressing. While offering certain advantages, such as higher data throughput, 7-bit addressing introduces disadvantages of its own when used in conjunction with the aforementioned address changing scheme utilizing fixed and variable address portions. More particularly, the number of possible addresses for supply items is reduced or limited since reducing the address size to 7 bits results in fewer bits available for use as variable address bits. For example, if 4 bits of the address were fixed, then the supply item would only have the 3 remaining bits as variable address bits, which translates to only eight possible addresses for supply items. Accordingly, an improved address-changing method for a shared bus system is desired. Patent literature US2013/054933A1 sets new component addresses by repeatedly applying an address-change operation derived from a consumable-specific characterisation value; US2010/306431A1 periodically updates unique slave addresses using synchronised master/slave addre