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EP-3803965-B1 - SILICON-ON-INSULATOR BACKSIDE CONTACTS

EP3803965B1EP 3803965 B1EP3803965 B1EP 3803965B1EP-3803965-B1

Inventors

  • GOKTEPELI, SINAN
  • IMTHURN, George Pete
  • CHU, Yun Han
  • LIANG, QINGQING

Dates

Publication Date
20260506
Application Date
20190507

Claims (13)

  1. An apparatus, comprising: a silicon-on-insulator, SOI, MOSFET having a diffusion region (314) as source or drain on a back insulating layer (302), wherein the diffusion region (314) has a front diffusion side (314f) and a back diffusion side (314b) opposite to the front diffusion side (314f), wherein the diffusion region (314) has a recess (334) at a selected recess area from the front diffusion side; a silicide layer (316) on the front diffusion side (314f) and on the recess (334) having a back silicide side facing the diffusion region (314) and a front silicide side opposite to the back silicide side, wherein a portion of the back silicide side touches the back insulating layer (302) under the selected recess area and another portion of the back silicide side does not touch the back insulating layer (302); and a backside contact (312, 332) connected to the silicide layer (316) by the portion of the back silicide side that touches the back insulating layer (302), wherein at least a portion of the backside contact is in the back insulating layer (302).
  2. The apparatus of claim 1, wherein the silicide layer is conforming with the front diffusion side.
  3. The apparatus of claim 1, further comprising a frontside contact connected to the silicide layer by the front silicide side.
  4. The apparatus of claim 3, further comprising one or more metal layers and vias coupled to the frontside contact.
  5. The apparatus of claim 1, further comprising one or more metal layers and vias coupled to the backside contact.
  6. The apparatus of claim 1, wherein the backside contact comprises Ti, W, Al, or Cu.
  7. The apparatus of claim 1, wherein the backside contact comprises a conductive diffusion barrier.
  8. The apparatus of claim 1, further comprising another diffusion region not coupled to any backside contacts.
  9. The apparatus of claim 1, further comprising another diffusion region not coupled to any frontside contacts.
  10. A method (600), comprising providing (602) an SOI wafer having a back insulating layer and one or more MOSFETs each having a diffusion region as source or drain, wherein the diffusion region has a front diffusion side and a back diffusion side; forming (604) a recess in a selected recess area in the diffusion region from the front diffusion side; forming (606) a silicide layer in the diffusion region from the front diffusion side and the recess, wherein the silicide layer has a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side, and wherein a portion of the back silicide side touches the back insulating layer under the selected recess area, and wherein another portion of the back silicide side does not touch the back insulating layer; forming (612) a contact opening in the back insulating layer; and forming (614) a backside contact in the contact opening, wherein the backside contact connects to the silicide layer under the selected recess area by the back silicide side.
  11. The method of claim 10, further comprising forming (608) a frontside contact connected to the silicide layer from the front silicide side.
  12. The method of claim 11, further comprising forming one or more metal layers and vias coupled to the frontside contact.
  13. The method of claim 10, further comprising forming (616) one or more metal layers and vias coupled to the backside contact.

Description

BACKGROUND Claim of Priority The present Application for Patent claims priority to Application No. 15/993,679 entitled "SILICON-ON-INSULATOR BACKSIDE CONTACTS" filed May 31, 2018, and assigned to the assignee hereof. Field Aspects of the present disclosure relate to silicon-on-insulator devices, and more particularly, to structures and manufacturing methods for silicon-on-insulator backside contacts. Background Silicon-on-insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of a conventional silicon substrate in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. An integrated circuit built using SOI devices may show processing speed that is approximately 30% faster than a comparable bulk-based integrated circuit and power consumption being reduced by as much as 80%, which makes it ideal for mobile devices. SOI chips also reduce the soft error rate, which is data corruption caused by cosmic rays and natural radioactive background signals. SOI transistors offer a unique opportunity for CMOS architectures to be more scalable. The buried oxide layer (back insulating layer) limits the punch-through that may exist on deep sub-micron bulk devices. In some examples, a layer transfer process is used to transfer a top active device portion of an SOI wafer to a handle wafer. In this process, the top portion of the SOI wafer is bonded to the handle wafer, and the bulk substrate layer (the sacrificial substrate) of the SOI wafer is removed. The process enables a backside connection system to be formed, in addition to a frontside connection system. For example, the back insulating layer may be thinned down. Openings may be formed in the back insulating layer so that backside contacts may be formed to connect to devices, such as a MOSFET's source, drain, and/or body. In addition, one or more metal layers and vias may be formed on the back insulating layer to route powers, grounds, and/or signals to the devices. The backside contacts and one or more metal layers and vias form the backside connection system as compared to frontside contacts and metal layers and vias in the frontside connection system. Source and drain silicide is often required to facilitate good connection between frontside or backside connection system with the devices. Conventionally, a dual-side silicidation process may be needed, forming a frontside silicide layer in the front of the source or drain for connection to the frontside connection system, and a backside silicide layer in the back of the source or drain for connection to the backside connection system. The backside silicide layer is formed after the formation of the devices and the frontside connection system. Consequently, forming the backside silicide layer may pose several issues. It increases process complexity, resulting in additional cost and yield loss. Higher thermal from extra silicidation process may have adverse effect on device performance and integrity of the frontside connection system. Accordingly, it would be beneficial to enable backside connection system without additional backside silicide layer. Attention is drawn to document US 2018/061766 A1 which relates to an integrated circuit device which includes only semiconductor devices with a same first polarity on one side of an insulator layer and only semiconductor devices with a different second polarity on an opposite side of the insulator layer to reduce size and complexity of the integrated circuit device as well as reducing the process steps associated with fabricating the integrated circuit device. Shared contacts between backside source/drain regions or spacers of the semiconductor devices with the first polarity and front-side source/drain regions or spacers of the semiconductor devices with the first polarity are used to connect the semiconductor devices on opposite sides of the insulator layer. Further attention is drawn to document US 9 711 501 B1 which relates to a semiconductor device. The semiconductor device includes a lower layer, an upper layer and an interlayer via. The lower layer includes a lower substrate, lower electronic devices, metallization elements and contact elements. One of the lower electronic devices includes a field effect transistor (FET), lower contacts and spacers interposed between the FET and the lower contacts. At least one of the contact elements is electrically coupled between a metallization element and one of the lower contacts to form a stack. The upper layer includes an upper substrate and upper electronic devices. One of the upper electronic devices includes an FET, upper contacts and spacers interposed between the FET and the upper contacts. The upper substrate and one of the upper contacts define a through-hole aligned with the stack. The interlayer via extends through the through-hole to electrically couple the stack and the one of the upper contacts.