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EP-3855482-B1 - ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND DESIGN ASSISTANCE METHOD FOR ELECTRONIC DEVICE

EP3855482B1EP 3855482 B1EP3855482 B1EP 3855482B1EP-3855482-B1

Inventors

  • KAWAI, KENICHI

Dates

Publication Date
20260506
Application Date
20180919

Claims (11)

  1. An electronic device comprising: a board (30) that includes an insulating film (32), a wiring layer (34) and a via (36) provided in the insulating film, and a plurality of power source pads (38b) and a plurality of ground pads (38a) which are provided in the insulating film so as to surround a capacitor region (42) in which a capacitor (40) is provided and to which a plurality of bumps (70) is coupled; and an electronic component (50) that is mounted at the board, and is electrically coupled to the plurality of power source pads (38b) and the plurality of ground pads (38a) through the wiring layer (34) and the via (36), wherein at least one of a case where the plurality of power source pads (38b) includes one or a plurality of first power source pads with which the via (36) is in contact and one or a plurality of second power source pads of which a total area in contact with the via (36) is smaller than a total area of the one or plurality of first power source pads in contact with the via (36) in a column (46) lined up along a side of an outline of the capacitor region so as to be adjacent to the capacitor region (42), and a case where the plurality of ground pads (38a) includes one or a plurality of first ground pads (38a1) with which the via (36) is in contact and one or a plurality of second ground pads (38a2) of which a total area in contact with the via is smaller than a total area of the one or plurality of first ground pads in contact with the via (36) in the column (46) lined up along the side of the outline of the capacitor region (42) so as to be adjacent to the capacitor region is satisfied.
  2. The electronic device according to claim 1, wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads (38a2) is not in contact with the via (36).
  3. The electronic device (100) according to claim 1 or 2, wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads (38a2) is arranged in a central portion of the side of the outline of the capacitor region (42), and is not arranged at ends of the side.
  4. The electronic device according to claim 1 or 2, wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads (38a2) is arranged from one end to the other end of the side of the outline of the capacitor region (42).
  5. The electronic device according to claim 1 or 2, wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads (38a2) is arranged so as to surround the capacitor region.
  6. The electronic device according to any one of claims 1 to 5, wherein the board (30) includes the wiring layer (34) electrically coupled to the one or plurality of second power source pads and the one or plurality of second ground pads (38a2) in the capacitor region (42) surrounded by the plurality of power source pads (38b) and the plurality of ground pads (38a), and the wiring layer (34) provided in the capacitor region (42) is not in contact with the via (36) in at least a partial region (48) of regions adjacent to the column (46).
  7. The electronic device according to claim 6, wherein a length of the at least a partial region (48) in a direction along the column (46) is longer than lengths of one power source pad of the plurality of power source pads (38b) and one ground pad of the plurality of ground pads (38a) in the direction along the column (46).
  8. The electronic device (100) according to claim 6 or 7, wherein a width of the at least a partial region (48) in a direction intersecting the direction along the column (46) is wider than 0 mm and equal to or narrower than 3.0 mm.
  9. The electronic device according to any one of claims 6 to 8, wherein the at least a partial region (48) is located so as to include a central portion of the side of the outline of the capacitor region (42).
  10. An electronic apparatus (100) comprising: a first board (10); a second board (30) that includes an insulating film (32), a wiring layer (34) and a via (36) provided in the insulating film, and a plurality of power source pads (38b) and a plurality of ground pads (38a) provided in the insulating film so as to surround a capacitor region (42) in which a capacitor (40) is provided, and is mounted at the first board (10) by a plurality of bumps (70) being coupled to the plurality of power source pads and the plurality of ground pads; and an electronic component (50) that is mounted at the second board (30), and is electrically coupled to the plurality of power source pads (38b) and the plurality of ground pads (38a) through the wiring layer (34) and the via (36), wherein at least one of a case where the plurality of power source pads (38b) includes one or a plurality of first power source pads with which the via (36) is in contact and one or a plurality of second power source pads of which a total area in contact with the via (36) is smaller than a total area of the one or plurality of first power source pads in contact with the via (36) in a column (46) lined up along a side of an outline of the capacitor region so as to be adjacent to the capacitor region (42), and a case where the plurality of ground pads (38a) includes one or a plurality of first ground pads (38a1) with which the via (36) is in contact and one or a plurality of second ground pads (38a2) of which a total area in contact with the via is smaller than a total area of the one or plurality of first ground pads in contact with the via (36) in the column (46) lined up along the side of the outline of the capacitor region so as to be adjacent to the capacitor region (42) is satisfied.
  11. A method for supporting a design of an electronic device that includes a board (30), which includes an insulating film (32), a wiring layer (34) and a via (36) provided in the insulating film, and a plurality of power source pads (38b) and a plurality of ground pads (38a) which are provided in the insulating film so as to surround a capacitor region (42) in which a capacitor (30) is provided and to which a plurality of bumps (70) is coupled, and an electronic component (50) which is mounted at the board and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via (36), the method comprising: by using a computer, obtaining magnitudes of currents flowing through the plurality of bumps (70); and correcting, when there is the bump of which the magnitude of the current exceeds a predetermined value among the plurality of bumps (70), design information of the board (30) such that the magnitudes of the currents flowing through the plurality of bumps are in the predetermined value by decreasing a total area with which at least one of the power source pads (38b) and the ground pads (38a) to which the bump exceeding the predetermined value is coupled is in contact with the via (36) among the plurality of power source pads (38b) and the plurality of ground pads (38a).

Description

Technical Field The embodiments discussed herein are related to an electronic device, an electronic apparatus, and a method for supporting a design of an electronic device. Background Art A method for coupling boards to each other by a bump such as a solder ball has been known. A method for improving uniformity of a current density in the solder ball by setting an area density of a via to be higher in a central region of a pad than in a peripheral region thereof so as to suppress formation of a void in the solder ball due to electromigration has been known (for example, PTL 1). Citation List Patent Literature PTL 1: Japanese Laid-open Patent Publication No. 2010-251754PTL 2: US Patent Application Publication No. US 2018/184524 A1, which relates to an integrated circuit package including a substrate; an integrated circuit chip arranged on the substrate; and a ball grid array army configured to electrically and mechanically connect a printed circuit board and the substrate, the ball grid array including: first solder balls that are periodically separated by a first pitch; and second solder balls that are periodically separated by a second pitch that is smaller than the first pitch, where a size of each solder ball of the first solder balls is substantially equal to a size of each solder ball of the second solder balls.PTL 3: US Patent Application Publication No. US 2006/103004 A1, which relates to a wiring board for a semiconductor integrated circuit package. PTL 3 discloses a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads. The ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.PTL 4: US Patent Application Publication No. US 2003/222356 A1, which relates to a semiconductor integrated circuit. The semiconductor package has a printed circuit board, a semiconductor chip mounted on a first surface of said printed circuit board, at least one power supply electrode on a second surface of said printed circuit board and connected to at least one power supply terminal of said semiconductor, and at least one ground electrode on a second surface of said printed circuit board and connected to at least one ground terminal of said semiconductor chip; a decoupling capacitor outside said semiconductor package and formed by a power supply plane connected to said power supply electrodes, and a ground plane connected to said ground electrodes; at least one power supply electrode pad connected to said power supply plane; and at least one ground electrode pad connected to said ground plane. Summary of Invention Technical Problem When a first board at which an electronic component is mounted is mounted at a second board by a plurality of bumps, currents may flow concentratedly to some bumps of the plurality of bumps. In this case, a current exceeding an allowable current may flow to the bump at which the current concentrates, and damage such as disconnection may occur. In one aspect, it is an object to relax concentration of currents on some bumps. Solution to Problem In one aspect, there is provided an electronic device including a board that includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads which are provided in the insulating film so as to surround a capacitor region in which a capacitor is provided and to which a plurality of bumps is coupled, and an electronic component that is mounted at the board, and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via. At least one of a case where the plurality of power source pads includes one or a plurality of first power source pads with which the via is in contact and one or a plurality of second power source pads of which a total area in contact with the via is smaller than a total area of the one or plurality of first power source pads in contact with the via in a column lined up along a side of an outline of the capacitor region so as to be adjacent to the capacitor region and a case where the plurality of ground pads includes one or a plurality of first ground pads with which the via is in contact and one or a plurality of second ground pads of which a total area in contact with the via is smaller than a total area of the one or plurality of first ground pads in contact with the via in the column lined up along the side of the outline of the capacitor region so as to be adjacent to the capacitor region is satisfied. In one aspect, there is provided an electronic apparatus including a first board, a second board that includes an insulating film, a wiring layer and a via provided in the insulating film, an