Search

EP-3903420-B1 - METHOD AND APPARATUS FOR A PHASE LOCKED LOOP CIRCUIT

EP3903420B1EP 3903420 B1EP3903420 B1EP 3903420B1EP-3903420-B1

Inventors

  • RAJ, MAYANK
  • TURKER MELEK, Didem, Z.
  • UPADHYAYA, PARAG
  • FRANS, YOHAN
  • CHANG, KUN-YUNG

Dates

Publication Date
20260513
Application Date
20200227

Claims (14)

  1. A phase locked loop, PLL, circuit (200), comprising: a multi-stage, differential, voltage controlled ring oscillator, VCO, (208); a first closed loop circuit (220) including a first loop filter (206), configured to receive a first signal (224) based on a feedback signal from the VCO and provide a first VCO frequency control signal (226) to the VCO; a second closed loop circuit (222) including a temperature compensation circuit (210) configured to provide a temperature-compensated second VCO frequency control signal (228) to the VCO; wherein the VCO comprises: delay elements (620) and first and second sets of varactors (602, 604); coarse frequency control circuitry (620, 640) configured to control a supply voltage (avcc_reg) and a reference voltage (avss_reg) of the delay elements; and fine frequency control circuitry (700) configured to control the first set of varactors based on the first VCO frequency control signal, and to control the second set of varactors based on a selectable one of the first VCO frequency control signal and the temperature-compensated second VCO frequency control signal.
  2. The PLL circuit (200) of claim 1, wherein a first bandwidth of the first closed loop circuit (220) is greater than a second bandwidth of the second closed loop circuit (222).
  3. The PLL circuit (200) of claim 2, wherein the first bandwidth is greater than the second bandwidth by at least 10 times the second bandwidth.
  4. The PLL circuit (200) of any of claims 1-3, wherein the temperature compensation circuit (210) includes: an operational amplifier (304) configured to generate a second signal (310) based on the first signal (224) and a reference signal (218); and a second loop filter (306) configured to generate the temperature-compensated second VCO frequency control signal (228) based on the second signal.
  5. The PLL circuit (200) of claim 4, wherein the second loop filter (306) is a low pass filter configured such that a first bandwidth of the first closed loop circuit (220) is greater than a second bandwidth of the second closed loop circuit (222).
  6. The PLL circuit (200) of any of claims 1-3 and 5, wherein the temperature-compensated second VCO frequency control signal (228) has a minimum voltage that is a ground voltage.
  7. The PLL circuit (200) of any of claims 1-3 and 5, wherein the coarse frequency control circuitry comprises: a supply voltage control circuity (620) to control the supply voltage (avcc_reg) of the delay elements based on a supply voltage (avcc) and a first multi-bit coarse control word (622); and a reference voltage control circuit (640) to control the reference voltage (avss_reg) of the delay elements based on a reference voltage (avss) and a second multi-bit coarse control word (642).
  8. The PLL circuit (200) of any of claims 1-3 and 5, further comprising a temperature-dependent voltage source (712) to provide a temperature-dependent voltage (710), wherein: the fine frequency control circuitry (700) comprises a current source control circuit (660) to control a current of the reference voltage (avss_reg) of the delay elements, wherein the current source control circuit (660) is controlled by a selectable one of the temperature-compensated second VCO frequency control signal (228) and the temperature-dependent voltage (710).
  9. The PLL circuit (200) of claim 7, wherein the fine frequency control circuitry (700) is controllable to operate in multiple modes that include: a first mode in which the second set of varactors (604) is controlled based on the first VCO frequency control signal (226 as Kvco2 608), and the regulated voltage (avss_reg) is controlled based on the temperature-dependent voltage (710 as Kvco3 662); a second mode in which the second set of varactors (604) is controlled based on the second VCO frequency control signal (228 as Kvco2 608), and the regulated voltage (avss_reg) is controlled based on the temperature-dependent voltage (710 as Kvco3 662); a third mode in which the second set of varactors (604) is controlled based on the first VCO frequency control signal (226 as Kvco2 608), and the regulated voltage (avss_reg) is controlled based on the temperature-compensated second VCO frequency control signal (228 as Kvco3 662); and a fourth mode in which the second set of varactors (604) is controlled based on the temperature-compensated second VCO frequency control signal (228 as Kvco2 608), and the regulated voltage (avss_reg) is controlled based on the second VCO frequency control signal (228 as Kvco3 662).
  10. A method, comprising: receiving, by a first loop filter (206) of a first closed loop circuit (220), a first signal (224) based on a feedback signal from a multi-stage, differential, voltage controlled ring oscillator, VCO, (208); providing, by the first loop filter, a first VCO frequency control signal (226) to the VCO; providing, by a temperature compensation circuit (210), a temperature-compensated second VCO frequency control signal (228) to the VCO; providing coarse frequency control of the VCO by controlling a supply voltage (avcc_reg) and a reference voltage (avss_reg) of delay elements of the VCO with coarse frequency control circuitry (620, 640); and providing fine frequency control of the VCO by controlling a first set of varactors (602) of the VCO based on the first VCO frequency control signal (226 as Kvco1 606), and by controlling a second set of varactors (604) of the VCO based on a selectable one of the first VCO frequency control signal (226 as Kvco2 608) and the second VCO frequency control signal (228 as Kvco2 608).
  11. The method of claim 10, further comprising: generating, by the compensation circuit (210), a second signal based on the difference between the first signal (224) and the reference signal (218); and generating, using a second loop filter of the compensation circuit, the second VCO frequency control signal based on the second signal.
  12. The method of claims 10 or 11, wherein the providing coarse frequency control comprises: controlling the supply voltage (avcc_reg) of the delay elements based on a supply voltage (avcc) and a first multi-bit coarse control word (622); and controlling the reference voltage (avss_reg) of the delay elements based on a reference voltage (avss) and a second multi-bit coarse control word (642).
  13. The method of any of claims 10 or 11, wherein the providing fine frequency control comprises: controlling a current source (660) of the reference voltage (avss_reg) of delay elements based on a selectable one of the temperature-compensated second VCO frequency control signal (228) and a temperature-dependent voltage (710).
  14. The method of claim 11, further comprising operating the fine frequency control circuitry (700) in one of multiple modes that comprise: a first compensation mode wherein the second VCO frequency control signal is configured to control one of a varactor (602-1, 602-2, 602-3) of the VCO and a current source of the VCO; a second compensation mode wherein the second VCO frequency control signal is configured to control the other of the varactor of the VCO and the current source of the VCO; a third compensation mode wherein the second VCO frequency control signal is configured to control both the varactor of the VCO and the current source of the VCO; and a fourth compensation mode where the third VCO frequency control signal is configured to control both the varactor of the VCO and the current source of the VCO.

Description

FIELD Examples of the present disclosure generally relate to integrated circuits ("ICs") and, in particular, to an embodiment related to temperature variation compensation for a phase locked loop (PLL) circuit. BACKGROUND Temperature variations typically have a significant impact on the locking process of a PLL circuit. During the operation of the PLL circuit, temperature changes (e.g., from -40 °C to 125 °C or vice-versa) may cause frequency drifts of the voltage controlled oscillator (VCO) of the PLL circuit. Typically, to compensation for those frequency drifts, the PLL circuit may move a VCO frequency control signal to bring the output frequency Fout of the VCO back to a required frequency (e.g., a reference frequency Fref x N). However, such a VCO frequency control signal may be outside the PLL circuit's charge pump's operation range, which may lead to a PLL lock failure. Accordingly, it would be desirable and useful to provide an improved method and system for temperature variation compensation in a PLL. US 2011/316595 A1 describes a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input. US 2009/039969 describes an oscillator including: a terminal receiving a first signal; a VCO coupled to the terminal, the VCO oscillating to generate a second signal and to change a frequency of the second signal in response to an amplitude of the first signal, and revealing gain-slope characteristics in the frequency of the second signal versus the amplitude of the first signal; and a control circuit coupled to the VCO to alter the gain-slope characteristics in response to the amplitude of the first signal, the VCO having so-called self regulating characteristics in which the VCO is locked up based on the variability of the manufactured ICs without depending on external control. SUMMARY The present invention are defined in the independent claims. Some additional features are defined in the dependent claims. According to a first aspect of the disclosure, there is provided a phase locked loop (PLL) circuit as is defined in claim 1. In some embodiments, a first bandwidth of the first closed loop circuit may be greater than a second bandwidth of the second closed loop circuit. In some embodiments, the first bandwidth may be greater than the second bandwidth by at least 10 times the second bandwidth. In some embodiments, the temperature compensation circuit may include an operational amplifier configured to generate a second signal based on the first signal and a reference signal. The temperature compensation circuit may also include a second loop filter configured to generate the temperature-compensated second VCO frequency control signal based on the second signal. In some embodiments, the second loop filter may be a low pass filter configured such that a first bandwidth of the first closed loop circuit is greater than a second bandwidth of the second closed loop circuit. In some embodiments, the second VCO frequency control signal may have a minimum voltage that is the same as a ground voltage. In some embodiments, the temperature-compensated second VCO frequency control signal may be configured to control at least one of a varactor of the VCO and a current source of the VCO to control an output frequency of the VCO. In some embodiments, the VCO may be configured to receive a third VCO frequency control signal from an open loop temperature dependent voltage circuit. In some embodiments, the fine frequency control circuit may be configured to select a compensation mode to control an output frequency of the VCO. The compensation mode may be selected from a first compensation mode, a second compensation mode, a third compensation mode, and a fourth compensation mode. In the first compensation mode, the second VCO frequency control signal may be configured to control one of a varactor of the VCO and a current source of the VCO. In the second compensation mode, the second VCO frequency control signal may be configured to control the other of the varactor of the VCO and the current source of the VCO. In the third compensation mode, the second VCO frequency control signal may be configured to control both the varactor of the VCO and the current source of the VCO. In the fourth compensation mode, the third VCO frequency co