EP-3929984-B1 - DISPLAY DEVICE INCLUDING PIXELS WITH DIFFERENT TYPES OF TRANSISTORS

EP3929984B1EP 3929984 B1EP3929984 B1EP 3929984B1EP-3929984-B1

Inventors

SONG, HEE RIM
KIM, HYUN JOON
KIM, HAE MIN
JUNG, MEE HYE

Dates

Publication Date: 20260506
Application Date: 20210622

Claims (13)

A display device, comprising: a substrate (SUB); a plurality of pixels (PXL) disposed on the substrate (SUB); a buffer layer (BFL) and first and second gate insulating layers (GI1, GI2) sequentially disposed on the substrate (SUB); first and second insulating layers (ILD1, ILD2) sequentially disposed on the first gate insulating layer (GI1); third and fourth insulating layers (ILD3_1, ILD3_2) sequentially disposed on the second gate insulating layer (GI2); and first to third conductive patterns (BML1 to BML3) disposed on the first insulating layer, the first to third conductive patterns (BML1 to BML3) being spaced apart from one another, wherein each of the plurality of pixels comprises: a light emitting element (OLED); a first scan line (Si) carrying an i th scan signal, wherein i is a positive integer; a second scan line (Si+1) carrying an (i+1) th scan signal; a data line (DLj) carrying a data signal; a power line (PL) carrying a driving power source; a reference voltage line (RFj) carrying a reference voltage; a first transistor (T1) controlling a current of the light emitting element; a second transistor (T2) connected between the data line (DLj) and a first gate electrode of the first transistor, the second transistor being turned on by the i th scan signal; a third transistor (T3) connected between the reference voltage line (RFj) and a first electrode of the first transistor, the third transistor being turned on by the (i+1) th scan signal; and a fourth transistor (T4) connected between the power line (PL) and a second electrode of the first transistor, the fourth transistor being turned off when an emission control signal is supplied to an emission control line,wherein the fourth transistor (T4) is a transistor of a type different from that of the first to third transistors, wherein the first conductive pattern (BML1) overlaps the first transistor (T1), the second conductive pattern (BML2) overlaps the second transistor (T2), and the third conductive pattern (BML3) overlaps the third transistor (T3), wherein each of the plurality of pixels further comprises a storage capacitor (Cst) including a lower electrode disposed on the first insulating layer and an upper electrode overlapping the lower electrode with the second and third insulating layers interposed therebetween, and wherein each of the first to third transistors (T1 to T3) is an oxide transistor and the fourth transistor (T4) is a poly-silicon transistor.
The display device of claim 1, wherein the first gate electrode of the first transistor (T1), a second gate electrode of the second transistor (T2), a third gate electrode of the third transistor (T3), and the first and second scan lines (Si, Si+1) are disposed on the third insulating layer, wherein a fourth gate electrode of the fourth transistor (T4) is disposed on the first gate insulating layer, wherein the second gate electrode of the second transistor (T2) is electrically connected to the second conductive pattern, and wherein the third gate electrode of the third transistor (T3) is electrically connected to the third conductive pattern.
The display device of claim 1 or 2, wherein the first transistor (T1) includes: a first active pattern disposed on the second insulating layer; the first gate electrode disposed on the third insulating layer; and the first electrode and the second electrode, respectively in contact with opposite end portions of the first active pattern, and/or wherein the first conductive pattern is electrically connected to the first electrode of the first transistor (T1) or the second electrodes of the first transistor (T1).
The display device of any of claim 1 to 3, wherein the lower electrode is integrally formed with the first conductive pattern and the upper electrode is integrally formed with the first gate electrode.
The display device of any of claims 1 to 4, each of the plurality of pixels further comprising an opening exposing a portion of the second insulating layer by removing a portion of the third insulating layer between the first gate electrode of the first transistor (T1) and the first conductive pattern, wherein the opening overlaps the first gate electrode of the first transistor (T1) and the first conductive pattern.
The display device of any of claims 1 to 3, wherein the reference voltage line (RFj), the data line (DLj), and the power line (PL) are disposed on the fourth insulating layer, wherein each of the plurality of pixels further comprises a connection line disposed on the fourth insulating layer, the connection line electrically connecting the third transistor (T3) and the light emitting element, and/or wherein the power line (PL) overlaps the first transistor (T1).
The display device of any of claims 1 to 6, wherein each of the plurality of pixels further comprising: a lower electrode disposed on the first gate insulating layer; and an upper electrode disposed on the fourth insulating layer, the upper electrode being electrically connected to the lower electrode through a first contact hole sequentially penetrating the second gate insulating layer and the first to fourth insulating layers, wherein the first gate electrode of the first transistor (T1) is disposed between the lower electrode and the upper electrode, and wherein the first conductive pattern is disposed between the lower electrode and the first gate electrode.
The display device of any of claims 1 to 7, wherein the lower electrode, the first conductive pattern, the first gate electrode, and the upper electrode overlap one another, wherein each of the plurality of pixels further comprises: first and second passivation layers sequentially disposed on the fourth insulating layer; and a first connection line disposed on the fourth insulating layer, the first connection line electrically connecting the third transistor (T3) and the light emitting element.
The display device of any of claims 1 to 8, wherein the reference voltage line (RFj) is disposed on the fourth insulating layer and the data line (DLj) and the power line (PL) are each disposed on the first passivation layer, wherein each of the plurality of pixels further comprises a bridge pattern disposed on the first passivation layer, the bridge pattern being spaced apart from each of the data line (DLj) and the power line (PL), and/or wherein the bridge pattern is electrically connected to the first connection line through a contact hole penetrating the first passivation layer.
The display device of any of claims, wherein each of the plurality of pixels further comprises a shielding member (SDL) disposed between the data line (DLj) and the first gate electrode of the first transistor (T1).
The display device of claim 10, wherein the shielding member (SDL) is disposed on the fourth insulating layer.
The display device of any of claims 1 to 11, wherein the fourth transistor(T4) includes; a fourth active pattern disposed on the buffer layer; the fourth gate electrode disposed on the first gate insulating layer; and first and second electrodes, respectively in contact with opposite end portions of the fourth active pattern, and/or wherein either the first electrode or the second electrode is electrically connected to the power line (PL) through a second connection line disposed on the fourth insulating layer.
The display device of any of claims 1 to 12, wherein the shielding member (SDL) is connected to either the first electrode or the second electrode through a contact hole sequentially penetrating the first and second gate insulating layers and the first to fourth insulating layers, electrically connecting the shielding member (SDL) to the power line (PL), wherein the driving power source applied to the power line (PL) is transferred to the shielding member (SDL), and/or wherein the shielding member (SDL) is electrically connected to the first electrode or the second electrode of the first transistor (T4).

Description

TECHNICAL FIELD The present disclosure generally relates to a display device including a pixel. DISCUSSION OF THE RELATED ART As display devices of higher resolutions for a given size are becoming more widely used, the structure of the circuitry for each pixel is becoming more complicated leading to potential problems in display quality such as capacitive coupling between data lines and gate electrodes of the pixel transistors. EP 3113226 A1 discloses a display device including different types of transistors. CN 108630147 A discloses a display device including scan lines carrying scan signals. US 20160379570 A1, WO 2020091165 A1 and US 20150170570 A1 discloses a display device including transistors. SUMMARY A display device is provided as defined in claim 1. The first gate electrode of the first transistor, a second gate electrode of the second transistor, a third gate electrode of the third transistor, and the first and second scan lines may be disposed on the third insulating layer. A fourth gate electrode of the fourth transistor may be disposed on the gate insulating layer. The second gate electrode of the second transistor may be electrically connected to the second conductive pattern, and the third gate electrode of the third transistor may be electrically connected to the third conductive pattern. The first transistor may include a first active pattern disposed on the second insulating layer. The first gate electrode may be disposed on the third insulating layer. The first electrode and the second electrode, respectively, may be in contact with both end portions of the first active pattern. The first conductive pattern may be electrically connected to one of the first and second electrodes of the first transistor. The display device may further include an opening exposing a portion of the second insulating layer by removing a portion of the third insulating layer between the first gate electrode of the first transistor and the first conductive pattern. The opening may overlap the first gate electrode of the first transistor and the first conductive pattern when viewed on a plane. The reference voltage line, the data line, and the power line may be disposed on the fourth insulating layer. The display device may further include a connection line disposed on the fourth insulating layer. The connection line may electrically connect the third transistor and the light emitting element to each other. The display device may further include a passivation layer disposed over the connection line. The light emitting element may include a first electrode disposed on the passivation layer. The first electrode may be electrically connected to the connection line through a contact hole. An emitting layer may be disposed on the first electrode. A second electrode may be disposed on the emitting layer. The power line may overlap the first transistor when viewed on a plane. The display device may further include a lower electrode disposed on the gate insulating layer and an upper electrode disposed on the fourth insulating layer. The upper electrode may be electrically connected to the lower electrode through a first contact hole sequentially penetrating the first to fourth insulating layers. The first gate electrode of the first transistor may be disposed between the lower electrode and the upper electrode. The first conductive pattern may be disposed between the lower electrode and the first gate electrode. The lower electrode, the first conductive pattern, the first gate electrode, and the upper electrode may overlap each other when viewed on a plane. The display device may further include first and second passivation layers sequentially disposed on the fourth insulating layer and a first connection line disposed on the fourth insulating layer. The first connection line may electrically connect the third transistor and the light emitting element to each other. The reference voltage line may be disposed on the fourth insulating layer, and the data line and the power line may be disposed on the first passivation layer. The display device may further include a bridge pattern disposed on the first passivation layer. The bridge pattern may be spaced apart from each of the data line and the power line. The bridge pattern may be electrically connected to the first connection line through a contact hole penetrating the first passivation layer. The light emitting element may include a first electrode disposed on the second passivation layer, the first electrode being electrically connected to the bridge pattern through a contact hole penetrating the second passivation layer. An emitting layer may be disposed on the first electrode. A second electrode may be disposed on the emitting layer. The display device may further include a shielding member located between the data line and the first gate electrode of the first transistor. The shielding member may be disposed on the fourth insulating layer. The fourth transistor may inc