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EP-3945607-B1 - SILICON CARBIDE DIODE WITH REDUCED VOLTAGE DROP, AND MANUFACTURING METHOD THEREOF

EP3945607B1EP 3945607 B1EP3945607 B1EP 3945607B1EP-3945607-B1

Inventors

  • RASCUNA', Simone
  • CHIBBARO, Claudio

Dates

Publication Date
20260506
Application Date
20210727

Claims (11)

  1. A Junction Barrier Schottky, JBS, diode (50), comprising: a solid body (52, 53) of silicon carbide having a surface (52a) and presenting a first conductivity type (N); a first implanted region (59') and a second implanted region (59'), which have a second conductivity type (P) and extend into the solid body (52, 53) in a direction (Z) starting from the surface (52a) and delimit between them a surface portion (64) of said solid body; Schottky-contact metal portions on the surface and in direct contact with the surface portion (64); and ohmic-contact metal portions on the surface and in direct contact with the first and second implanted regions (59'), wherein the solid body (52, 53) comprises an epitaxial layer (52) including said surface portion (64) and a bulk portion, the surface portion extending over the bulk portion, wherein the surface portion (64) houses a plurality of doped sub-regions (64a-64c), which extend in succession one after another in said direction (Z), each having the first conductivity type (N) and a respective conductivity level higher than that of the bulk portion, wherein said doped sub-regions (64a-64c) are layered, thus forming a stack of doped layers that follow one another in said direction (Z), wherein: said plurality of doped sub-regions (64a-64c) includes: a first sub-region (64a), which extends into the epitaxial layer (52) starting from the surface (52a); a second sub-region (64b), which extends in the epitaxial layer (52) adjacent, along said direction (Z), to the first sub-region (64a); and a third sub-region (64c), which extends in the epitaxial layer (52) adjacent, along said direction (Z), to the second sub-region (64b), said doped sub-regions (64a-64c) having a respective electrical conductivity level such that the second sub-region (64b) has an electrical conductivity higher than the first sub-region (64a) and the third sub-region (64c), wherein the conductivity level of the first sub-region (64a) at the surface is higher than that of the bulk portion.
  2. The JBS diode according to claim 1, wherein: the first sub-region (64a) has a doping level comprised between 1·10 16 at/cm 3 and 1·10 17 at/cm 3 ; the second sub-region (64b) has a doping level comprised between 1·10 17 at/cm 3 and 1·10 20 at/cm 3 ; and the third sub-region (64c) has a doping level comprised between 1·10 16 at/cm 3 and 1·10 17 at/cm 3 .
  3. The JBS diode according to any one of the preceding claims, wherein the sum of the thicknesses of the first, second, and third sub-regions (64a-64c) is equal to or less than the thickness, in said direction (Z), of each one of the first and second implanted regions (59').
  4. The JBS diode according to anyone of the preceding claims, wherein the material of the solid body is one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC.
  5. The JBS diode according to anyone of the preceding claims, said epitaxial layer (52) being a drift layer of said JBS diode.
  6. A method for manufacturing a Junction Barrier Schottky, JBS, diode (50), comprising the steps of: providing a solid body (52, 53) of silicon carbide having a surface (52a) and presenting a first conductivity type (N); forming in the solid body (52, 53), by implantation of doping agents having a second conductivity type (P), a first implanted region (59') and a second implanted region (59'), which each extend in a direction (Z) starting from the surface (52a) and delimit between them a surface portion (64) of said solid body; forming Schottky-contact metal portions on the surface (52a) and in direct contact with the surface portion (64); and forming ohmic-contact metal portions on the surface (52a) and in direct contact with the first and second implanted regions (59'), wherein the solid body (52, 53) comprises an epitaxial layer (52) including said surface portion (64) and a bulk portion, the surface portion extending over the bulk portion, wherein the method further comprises the steps of forming in the surface portion (64), by respective implantations of doping agents having the first conductivity type (N), a plurality of doped sub-regions (64a-64c) which extend in succession one after another in said direction (Z), each having a respective conductivity level higher than that of the bulk portion, wherein said doped sub-regions (64a-64c) are implanted in the form of layers, thus forming a stack of doped layers that follow one another in said direction (Z), wherein forming said plurality of doped sub-regions (64a-64c) includes: forming a first sub-region (64a) in the epitaxial layer (52) starting from the surface (52a); forming a second sub-region (64b) in the epitaxial layer (52) adjacent, along said direction (Z), to the first sub-region (64a); and forming a third sub-region (64c), which extends in the epitaxial layer (52) adjacent, along said direction (Z), to the second sub-region (64b), wherein said implantations are designed in such a way that the second sub-region (64b) has a conductivity higher than the first sub-region (64a) and the third sub-region (64c), wherein the conductivity level of the first sub-region (64a) at the surface is higher than that of the bulk portion.
  7. The method according to claim 6, wherein: forming the first sub-region (64a) includes carrying out a first implantation with an energy comprised between 10 keV and 20 keV; and forming the second and third sub-regions (64b, 64c) includes carrying out a second implantation with an energy comprised between 150 keV and 250 keV.
  8. The method according to claim 6 or claim 7, wherein: forming the first sub-region (64a) includes carrying out a first implantation with an implantation dose comprised between 1.0·10 11 and 1.0·10 13 at/cm 2 ; and forming the second and third sub-regions (64b, 64c) includes carrying out a second implantation with an implantation dose comprised between 1.0·10 13 and 1.0·10 15 at/cm 2 .
  9. The method according to anyone of claims 6-8, wherein the first, second, and third sub-regions (64a-64c) are formed in such a way that the sum of the thicknesses of the first, second, and third sub-regions (64a-64c) is equal to or less than the thickness, in said direction (Z), of each one of the first and second implanted regions (59').
  10. The method according to anyone of claims 6-9, wherein the material of the solid body is one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC.
  11. The method according to anyone of claims 6-10, said epitaxial layer (52) being a drift layer of said JBS diode.

Description

The present invention relates to an electronic device of silicon carbide (SiC) and to a manufacturing method thereof. On the market, switching devices have recently been proposed known as JBS (Junction Barrier Schottky) diodes or MPS (Merged PiN Schottky) diodes. These devices are generally of a SiC substrate and comprise implanted areas having a conductivity opposite to that of the substrate (e.g., of a P type for a substrate of an N type). In these devices, two distinct types of contacts are present: an ohmic one in the implanted areas, and a Schottky one in the areas comprised between the implanted areas. The above characteristics render JBS diodes particularly suited to working in high-voltage power devices. Figure 1 shows, in lateral sectional view in a (triaxial) cartesian reference system of axes X, Y, Z, an MPS device 1 of a known type. The MPS device 1 includes: a substrate 3, of SiC of an N type, having a first dopant concentration, provided with a surface 3a opposite to a surface 3b, and having a thickness equal to approximately 350 µm; a drift layer (grown epitaxially) 2, of SiC of an N type, having a second dopant concentration lower than the first dopant concentration, which extends over the surface 3a of the substrate 3 and has a thickness comprised between 5 and 15 µm; an ohmic-contact region 6 (for example, of nickel silicide), which extends over the surface 3b of the substrate 3; a cathode metallization 16, which extends over the ohmic-contact region 6; an anode metallization 8, which extends over a top surface 2a of the drift layer 2; multiple junction-barrier (JB) elements 9 in the drift layer 2, which face the top surface 2a of the drift layer 2 and each include a respective implanted region 9' of a P type and an ohmic contact 9" of metal material; and an edge-termination region, or protection ring, 10 (optional), in particular an implanted region of a P type, which completely surrounds the junction barrier (JB) elements 9. Schottky diodes 12 are formed at the interface between the drift layer 2 and the anode metallization 8. In particular, Schottky junctions (i.e., semiconductor-metal junctions) are formed by portions of the drift layer 2 in direct electrical contact with respective portions of the anode metallization 8. The region of the MPS device 1 that includes the JB elements 9 and the Schottky diodes 12 (i.e., the region contained within the protection ring 10) is an active area 4 of the MPS device 1. At the basis of the design of JBS or MPS devices there is creation of a potential barrier designed to protect the metal/SiC Schottky junctions from high electrical fields generated in the SiC substrate. For this purpose, integrated in the drift layer 2 are the P implants 9', which laterally delimit surface portions of an N type, located close to one another, of the SiC drift layer 2. With deposition of the metallization 8 on the top surface of the drift layer 2, Schottky junctions are formed in parallel with PN junctions. In a forward-biased JBS device, the current flows in the non-depleted Schottky regions comprised between the P implants 9', preserving the unipolar operating mode. In reverse biasing, conduction between the Schottky regions is suppressed by the pinch-off effect of the adjacent PN junctions. The reverse-biasing characteristic of the JBS device substantially corresponds to that of a PN junction. It is evident that the distance d (in the direction X of Figure 1) between the P implants 9' must be chosen in an appropriate way to optimize the trade-off between the potential drop in the ON state (which increases with the reduction of said distance d) and the current losses (which decrease with the reduction of said distance d). It is of fundamental importance to minimize the losses in conduction in discrete power devices in order to reduce the energy consumption of the circuits in which said devices are used. For this reason, the possibility of controlling the SBH (Schottky-Barrier Height) value is particularly important for controlling the potential drop of Schottky diodes. In particular, the reduction of the SBH value produces a significant reduction of the potential drop. However, the reduction of the SBH value presents the disadvantage of causing a substantial increase in the leakage current in reverse biasing. The distance between the P+ implants 9' must consequently be carefully designed. A prior-art solution is provided by US2015/0372093, where a switching device is described, such as a JBS (Junction Schottky Barrier) diode, which has a solid body of silicon carbide of an N type, housing implanted regions of a P type (similar to the regions 9' of Figure 1). The P implanted regions extend in the solid body starting from a surface thereof and delimit, between them, N+ doped surface portions, i.e., ones having a doping density higher than that of the bulk of the solid body. By modulating the surface concentration of the solid body through the aforementioned N+ implant