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EP-3948344-B1 - EVENT DRIVEN SHARED MEMORY PIXEL

EP3948344B1EP 3948344 B1EP3948344 B1EP 3948344B1EP-3948344-B1

Inventors

  • HENDERSON, ROBERT
  • FINKELSTEIN, HOD

Dates

Publication Date
20260506
Application Date
20200501

Claims (14)

  1. A Time of Flight, TOF, system (100), comprising: an incrementing circuit; and a plurality of pixels, each pixel comprising: a plurality of detectors (110d) configured to output respective detection signals responsive to detection of a plurality of photons incident thereon; and a shared memory; characterized in that the shared memory is configured to store a respective count of the photons incident on each of the plurality of detectors, wherein the incrementing circuit is configured to update the respective count for each of the plurality of detectors in the shared memory based on the respective detection signals, wherein respective ones of the plurality of pixels further comprise a bus arbiter (325, 620) that controls access to the shared memory by the plurality of detectors of the pixel and the bus arbiter is configured to receive a plurality of requests from multiple ones of the plurality of detectors for access to the shared memory and, responsive thereto, select one detector of the plurality of detectors to be given access to the shared memory.
  2. The TOF system of Claim 1, wherein the shared memory comprises a plurality of bins, and wherein a subset of the plurality of bins is associated with a first detector of the plurality of detectors, and each bin of the subset is configured to store the respective count of the photons incident on the first detector during a time period.
  3. The TOF system of Claim 2, further comprising a bin sampling circuit configured to select a first bin from among the subset of the plurality of bins into which the respective count of the photons incident on the first detector is stored.
  4. The TOF system of Claim 3, wherein the bin sampling circuit is further configured to be activated responsive to detection of the photons by the first detector.
  5. The TOF system of Claims 3 or 4, wherein the bin sampling circuit is further configured to be held in reset by the first detector prior to the first detector detecting the photons.
  6. The TOF system of any one of the preceding claims, wherein the incrementing circuit is further configured to update the respective count for each of the plurality of detectors in the shared memory responsive to the respective detection signals output by one or more of the plurality of detectors.
  7. The TOF system of any one of the preceding claims, wherein the incrementing circuit is an arithmetic logic unit (ALU) that is shared among the plurality of pixels.
  8. The TOF system of Claim 7, wherein the ALU is configured to perform a read- increment-write operation on the shared memory of each of the pixels.
  9. The TOF system of any of the preceding claims, wherein: at least one of the plurality of detectors is a Single Photon Avalanche Diode (SPAD); or the incrementing circuit is further configured to update the respective count for each of the plurality of detectors for each of the plurality of pixels; or at least one of the pixels has an area of less than 10 µm by 10 µm; or at least one of pixels has an area of less than 3 µm by 3 µm; or at least one of the pixel has a full-well depth of at least 10000 photons; or the shared memory is a static random access memory (SRAM) or a dynamic random access memory (DRAM); or the incrementing circuit comprises a Linear Feedback Shift Register (LFSR).
  10. The TOF system of any of the preceding claims, wherein the TOF system comprises a plurality of tiers, wherein a first tier of the plurality of tiers comprises the detectors; and wherein a second tier of the plurality of tiers comprises the shared memory.
  11. The TOF system of Claim 3, wherein the incrementing circuit is configured to update the respective count of the photons incident on the first detector in the shared memory at the first bin in the shared memory indicated by the bin sampling circuit.
  12. The TOF system of Claim 1 or 2 or 11, wherein the incrementing circuit is configured to update the respective count for each of the plurality of detectors in the shared memory based on a comparison of the respective count to a threshold value.
  13. The TOF system of Claim 12, wherein the threshold value is based on a background level of light associated with a field of view of the ToF system, a capacity of the shared memory, and/or a saturation level of digital conversion circuitry associated with the TOF system.
  14. The TOF system of Claim 13, wherein the incrementing circuit is further configured to associate a respective counter with each bin of the subset of the plurality of bins and to update the counter based on whether the respective count of the photons incident on the first detector during the time period exceeds the threshold value.

Description

CLAIM OF PRIORITY FIELD The present disclosure is directed to lidar systems, and more particularly, to methods and devices to provide shared memory in pixels of time-of- flight lidar systems. BACKGROUND Time of flight (ToF) based imaging is used in a number of applications including range finding, depth profiling, and 3D imaging (e.g., Light Detection And Ranging (LIDAR), also referred to herein as lidar). ToF 3D imaging systems can be categorized as indirect ToF (iToF) or direct ToF systems. Direct ToF measurement includes directly measuring the length of time between emitting radiation by emitter element(s) of a LIDAR system, and sensing the radiation after reflection from an object or other target (also referred to herein as an echo signal) by detector element(s) of the LIDAR system. From this length of time, the distance to the target can be determined. Indirect ToF measurement includes modulating the amplitude of the signals emitted by the emitter element(s) and measuring phases (e.g., with respect to delay or shift) of the echo signals received at the detector element(s). These phases may be measured with a series of separate measurements or samples. The results of these measurements produce multiple (e.g., two) vector components, the angle formed by these components is the phase angle. The distance d to the target can be calculated from the detected phase shift of the returning echo signal: d=ct2=φ2πc2fm where c is the speed of light, t is the time required for a photon to travel to the target and back to the detector, phi (φ) is the phase shift of the modulated signal and fm is the modulation frequency of the emitted signal. Both direct and indirect ToF systems may utilize memory bins for distance calculation. For example, direct ToF systems may collect counts of arriving photons in some number of histogram bins which may be used to calculate the distance directly. Indirect ToF may also utilize bin storage as part of its distance calculation. Because indirect ToF systems may calculate a target's distance based on a finite number of phase measurements, indirect ToF systems may utilize fewer bins than direct ToF systems in some embodiments (e.g., at 0°, 90°, 180°, 270°, etc.). SUMMARY According to an embodiment of the present invention, a Time of Flight (TOF) system according to claim 1 is provided. Advantageous embodiment are provided in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is an example lidar system according to some embodiments described herein.FIG. 1B is an example of a control circuit that generates emitter and/or detector control signals according to some embodiments described herein.FIG. 2 is a schematic view comparing relative sizing and configuration of SPAD-based pixels, including pixels according to some embodiments of the present invention.FIG. 3 is a schematic block diagram of a SPAD-based pixel architecture incorporating a shared SRAM according to some embodiments of the present invention.FIG. 4 is a schematic block diagram of another SPAD-based pixel architecture incorporating a shared SRAM according to some embodiments of the present invention.FIG. 5 is a schematic block diagram of another SPAD-based pixel architecture incorporating a shared SRAM according to some embodiments of the present invention.FIG. 6 is a schematic diagram of an additional example of an implementation of a single bin pixel incorporating shared SRAM according to some embodiments of the present invention.FIG. 7 is a schematic diagram of an example of a pixel array, according to some embodiments of the present invention.FIG. 8 illustrates an example readout timing of the Din signal according to embodiments described herein.FIGS. 9 to 11 illustrate example pixel configurations according to embodiments described herein.FIG. 12 is a schematic diagram of an ALU that may be shared to an individual pixel according to embodiment described herein.FIG. 13 is a timing diagram illustrating operations of a pixel according to embodiments described herein.FIGS. 14A and 14B are schematic diagrams illustrating an offset sampler and a modification thereto, according to some embodiments described herein.FIGS. 15A to 15C are schematic diagrams illustrating an offset sampler and a modification thereto, according to some embodiments described herein.FIG. 16 is a schematic diagram of a true single-phase clock (TSPC) flip-flop sampler, according to some embodiments described herein.FIG. 17A illustrates an example embodiment of a shared ALU in-pixel timing generator, according to embodiments described herein. FIGS. 17B and 17C are timing diagrams of signals associated with the ALU in-pixel timing generator of FIG. 17A.FIG. 18 is a schematic diagram of an example embodiment of a 1-bin pixel with rolling SRAM read-increment-write, according to some embodiments described herein.FIG. 19 is a block diagram illustrated an example of a tiered embodiment of a tiered memory structure.FIGS. 20A to 20C are schematic diagra