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EP-3968367-B1 - OPTIMAL SIGNAL ROUTING PERFORMANCE THROUGH DIELECTRIC MATERIAL CONFIGURATION DESIGNS IN PACKAGE SUBSTRATE

EP3968367B1EP 3968367 B1EP3968367 B1EP 3968367B1EP-3968367-B1

Inventors

  • QIAN, Zhiguo
  • DUAN, GANG
  • AYGÜN, Kemal
  • KONG, Jieying

Dates

Publication Date
20260506
Application Date
20200318

Claims (11)

  1. A semiconductor package (100), comprising: a package substrate (103); a plurality of dielectric regions in the package substrate (103), wherein the plurality of dielectric regions include a high Dk region (131), a low Dk region (132), and a dielectric region (130), wherein the high Dk region (131) has a dielectric constant higher than the dielectric region (130), wherein the low Dk region (132) has a dielectric constant lower than the dielectric region (130), and wherein the dielectric region (130) has a dielectric constant of a substrate build-up material; and a die (105) on the package substrate (103), wherein the die (105) has a first edge with a first single-ended input/output, I/O, routing region (107), and a second edge with a second differential I/O routing region (108), wherein the first single-ended I/O routing region (107) of the first edge is opposite to the second differential I/O routing region (108) of the second edge, and wherein the high Dk region (131) includes the first single-ended I/O routing region (107), and the low Dk region (132) includes the second differential I/O routing region (108).
  2. The semiconductor package (100) of claim 1, further comprising: a first conductive layer (310) in a first dielectric; a second dielectric over the first dielectric; a second conductive layer (311) in the second dielectric, wherein the second conductive layer (311) includes a plurality of first traces and a plurality of second traces, wherein the plurality of first traces are positioned in the first single-ended I/O routing region (107), and wherein the plurality of second traces are positioned in the second differential I/O routing region (108); a third conductive layer (312) over the second dielectric; and the high Dk region (131) and the low DK region (132) in the first and second dielectrics, wherein the high Dk region (131) surrounds the plurality of first traces, and wherein the low Dk region (132) surrounds the plurality of second traces.
  3. The semiconductor package (100) of claim 2, the high Dk region (131) is between the first conductive layer (310) and the third conductive layer (312).
  4. The semiconductor package (100) of claim 2 or 3, the low Dk region (132) is between the first conductive layer (310) and the third conductive layer (312).
  5. The semiconductor package (100) of claim 2, 3 or 4, wherein the dielectric region (130) is in the first and second dielectrics, wherein the dielectric region (130) separates the high Dk region (131) and the low Dk region (132).
  6. The semiconductor package (100) of claim 5, the high Dk region (131) includes a first material having a first Dk value, wherein the dielectric region (130) includes a second material having a second Dk value, wherein the low Dk region (132) includes a third material having a third Dk value, wherein the first Dk value of the high Dk region (131) is greater than the third Dk value of the low Dk region (132), and wherein the second Dk value of the first and second dielectrics is between the first Dk value and the third Dk value.
  7. The semiconductor package (100) of claim 6, wherein the third Dk value is between 3.3 and 3.5.
  8. The semiconductor package (100) of one of the claims 2 - 7, wherein the plurality of first traces are a plurality of single-ended routing traces, and wherein the plurality of second traces are a plurality of differential routing traces.
  9. The semiconductor package (100) of claim 8, wherein the plurality of single-ended routing traces (111a) have a width and a line spacing that is lower than a width and a line spacing of the plurality of differential routing traces (111b).
  10. The semiconductor package (100) of one of the claims 2 - 9, further comprising a plurality of vias in the first and second dielectrics, wherein the plurality of vias couple a conductive pad of the second conductive layer (311) to the first and second conductive layers.
  11. A method of forming a semiconductor package, comprising: forming a plurality of dielectric regions in a package substrate, wherein the plurality of dielectric regions include a high Dk region, a low Dk region, and a dielectric region, wherein the high Dk region has a dielectric constant higher than the dielectric region, wherein the low Dk region has a dielectric constant lower than the dielectric region, and wherein the dielectric region has a dielectric constant of a substrate build-up material; and attaching a die on the package substrate, wherein the die has a first edge with a first input/output, I/O, routing region, and a second edge with a second I/O routing region, wherein the first I/O routing region of the first edge is opposite to the second I/O routing region of the second edge, and wherein the high Dk region includes the first I/O routing region, and the low Dk region includes the second I/O routing region.

Description

FIELD Embodiments relate to packaging semiconductor devices. More particularly, the embodiments relate to package substrates with different dielectric constant (Dk) regions. BACKGROUND For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor devices. The drive to scale these ICs, including package substrates, while optimizing the performance of each device, however, is not without issue. Existing technologies typically implement package substrates with the same dielectric material and thickness across each of the dielectric layers. These package substrates also include conductive routings for both differential and single-ended input/output (I/O) interfaces. The routings of the package substrates further include different routing segments like a breakout routing and a main routing. These routing segments, however, typically have different - or even conflicting - routing demands for the substrate's dielectric material and stack-up configurations. Accordingly, due to conflicting packaging and routing demands, the existing package substrates compromise the signal performance of the different routing segments and interfaces. US 2007 / 102 806 A1 discloses a PCB composed of copper planes and, with copper plane being attached to underlying substrate, which is typically fiberglass but could also be a flexible substrate material. One plane is a voltage plane, while the other plane is a ground plane. Sandwiched between planes and is a dielectric layer composed of material with varying dielectric constant. Two dielectric materials and are used in the dielectric layer. Dielectric material has a relatively high while dielectric material has a relatively low dielectric constant. Pins are connected to the voltage plane and the ground plane. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments described herein illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar features. Furthermore, some conventional details have been omitted so as not to obscure from the inventive concepts described herein. Figure 1 is an illustration of a plan and cross-sectional view of a semiconductor package with a package substrate that includes a single-ended input/output (I/O) interface, a differential I/O interface, and a plurality of dielectric constant (Dk) regions within a dielectric, according to one embodiment.Figures 2A - 2C are illustrations of perspective views of a process flow to form a semiconductor package with a package substrate that includes a single-ended I/O interface, a differential I/O interface, and a plurality of Dk regions within a dielectric, according to some embodiments.Figures 3A - 3D are illustrations of cross-sectional views of a process flow using a pick and place method to form a semiconductor package with a package substrate that includes a single-ended I/O interface, a differential I/O interface, and a plurality of Dk regions within a dielectric, according to some embodiments.Figures 4A - 4G are illustrations of cross-sectional views of a process flow to form a semiconductor package with a package substrate that includes a single-ended I/O interface, a differential I/O interface, a photoimageable dielectric, and a plurality of Dk regions within a dielectric, according to some embodiments.Figure 5 is an illustration of a schematic block diagram illustrating a computer system that utilizes a semiconductor package with a package substrate that includes a single-ended I/O interface, a differential I/O interface, and a plurality of Dk regions within a dielectric, according to one embodiment. DETAILED DESCRIPTION Described herein are semiconductor packages with different dielectric constant (Dk) regions within a single dielectric layer and methods of forming such semiconductor packages. The semiconductor packages described below and methods of forming such semiconductor packages include a package substrate with a single-ended input/output (I/O) interface (or bus), a differential I/O interface, and a plurality of Dk regions within a dielectric (or a dielectric layer), according to some embodiments. For example, as described below in some embodiments, the package substrate may have a single routing layer with single-ended routing traces and differential routing traces, where the single-ended routing traces are surrounded with a higher Dk region (or a high-k dielectric region) and the differential routing traces are surrounded with a lower Dk region (or a low-k dielectric region). For some embodiments, the dielectric materials of the high and low Dk regions may surround (or embed) the routing traces below and above the routing layer at the designated respective regions. As described herein, a "high-k dielectric" refers to