Search

EP-3996140-B1 - DISPLAY PANEL, DRIVE METHOD THEREFOR, AND DISPLAY DEVICE

EP3996140B1EP 3996140 B1EP3996140 B1EP 3996140B1EP-3996140-B1

Inventors

  • HU, YE
  • DIAO, KAI
  • HOU, QINGNA
  • XIE, Hongzhou
  • ZHENG, SHANGTAO
  • YU, RENHUI
  • ZHA, Wen
  • CHEN, XIN
  • CHEN, Meizhen

Dates

Publication Date
20260506
Application Date
20200515

Claims (13)

  1. A display panel, comprising a display region (110) and a non-display region (120), wherein the display region (110) comprises a plurality of gate lines (111) extending in a first direction and a plurality of data lines (112) extending in a second direction, and the plurality of gate lines (111) intersect the plurality of data lines (112) to define a plurality of pixel regions; the non-display region (120) comprises at least one first bonding region (210) located on one side of the display region (110), and further comprises first connection lines (220) connected to the plurality of gate lines (111) respectively and second connection lines (230) connected to the plurality of data lines (112) respectively; at least a part of each first connection line (220) and at least a part of each second connection line (230) are used for bonding connection, and the part of each first connection line (220) and the part of each second connection line (230) used for bonding connection are located in the first bonding region (210); the display panel further comprises at least one chip on film (240), the chip on film (240) comprises a second bonding region (241) bonded to the first bonding region (210), and further comprises a first region (242) and a second region (243) located between the second bonding region (241) and the first region (242); the chip on film (240) is folded to a back surface of the display panel; a scanning driving integrated circuitry (250) and a data driving integrated circuitry (260) are bonded in the first region (242), the scanning driving integrated circuitry (250) being connected to the second bonding region (241) and configured to transmit a scanning signal to first bonding electrodes (291) of the second bonding region (241) via respective first wirings (251), and the data driving integrated circuitry (260) being connected to the second bonding region (241) and configured to transmit a data signal to second bonding electrodes (292) of the second bonding region (241) via respective second wirings (261); the first wirings (251) and the second wirings (261) are arranged at different layers in the second region (243); the second bonding region (241) comprises a plurality of repetition units (246), and each repetition unit (246) comprises a first low level signal electrode (293), at least one of said first bonding electrodes (291) and at least oneof said second bonding electrodes (292), wherein the first low level signal electrode (293) is to prevent the scanning signal on a first bonding electrode (291) from being coupled to the data signal on a second bonding electrode (292); and the chip on film (240) further comprises first low level signal lines (290) connected to the first low level signal electrodes (293) respectively, wherein any of the first low level signal lines (290) either is arranged at a same layer as the first wirings (251) in the second region (243) and electrically connected to the scanning driving integrated circuitry (250); or is arranged at a same layer as the second wirings (261) in the second region (243) and electrically connected to the data driving integrated circuitry (260).
  2. The display panel according to claim 1, wherein the first bonding electrodes (291) are connected to the first wirings (251) respectively, the second bonding electrodes (292) are connected to the second wirings (261) respectively, and the first bonding electrodes (291) and the second bonding electrodes (292) are located on a same side of the chip on film (240).
  3. The display panel according to claim 2, wherein the plurality of bonding electrodes is located on the same side of the chip on film (240) as the scanning driving integrated circuitry (250) and the data driving integrated circuitry (260); a third wiring (270) is located on the same side of the chip on film (240) as the scanning driving integrated circuitry (250) and the data driving integrated circuitry (260); the chip on film (240) further comprises a third region (244) located between the first region (242) and the second region (243) and a fourth region (245) located between the second bonding region (241) and the second region (243), the third region (244) is provided with a first via hole (2441), and the fourth region (245) is provided with a second via hole (2451); a fourth wiring (280) comprises a first segment (281) connected to the second bonding region (241), a second segment (282) connected to a target driving integrated circuitry and a third segment (283) connected to the second segment (282) through the first via hole (2441) and connected to the first segment (281) through the second via hole (2451), and the second segment (282) and the third segment (283) are located on the same side of the chip on film (240) as the third wiring (270); and the third wiring (270) is the first wiring (251), the fourth wiring (280) is the second wiring (261), and the target driving integrated circuitry is the data driving integrated circuitry (260); or the third wiring (270) is the second wiring (261), the fourth wiring (280) is the first wiring (251), and the target driving integrated circuitry is the scanning driving integrated circuitry (250).
  4. The display panel according to claim 2, wherein the scanning driving integrated circuitry (250) and the data driving integrated circuitry (260) are located on a same side of the chip on film (240), and the plurality of bonding electrodes is located on the other side of the chip on film (240); the chip on film (240) further comprises a third region (244) located between the first region (242) and the second region (243) and a fourth region (245) located between the second bonding region (241) and the second region (243), the third region (244) is provided with a first via hole (2441), and the fourth region (245) is provided with a second via hole (2451); a third wiring (270) comprises a first segment (271) connecting a first driving integrated circuitry and the second via hole (2451), and a second segment (272) connecting the first segment (271) and the second bonding region (241) through the second via hole (2451); a fourth wiring (280) comprises a third segment (281) connecting the second bonding region (241) and the first via hole (2441) and a fourth segment (282) connecting the third segment (281) and a second driving integrated circuitry through the first via hole (2441), and the first segment (271) and the third segment (281) are arranged at different layers; and the third wiring (270) is the first wiring (251), the fourth wiring (280) is the second wiring (261), the first driving integrated circuitry is the scanning driving integrated circuitry (250), and the second driving integrated circuitry is the data driving integrated circuitry (260); or the third wiring (270) is the second wiring (261), the fourth wiring (280) is the first wiring (251), the first driving integrated circuitry is the data driving integrated circuitry (260), and the second driving integrated circuitry is the scanning driving integrated circuitry (250).
  5. The display panel according to claim 2, wherein the plurality of bonding electrodes and a first driving integrated circuitry are located on the same side of the chip on film (240), and a second driving integrated circuitry is located on the other side of the chip on film (240); a third wiring (270) is located on the same side of the chip on film (240) as the plurality of bonding electrodes and the first driving integrated circuitry; the chip on film (240) further comprises a third region (244) located between the first region (242) and the second region (243) and a fourth region (245) located between the second bonding region (241) and the second region (243), and the fourth region (245) is provided with a third via hole (2451); a fourth wiring (280) comprises a first segment (281) connecting the second driving integrated circuitry and the third via hole (2451) and a second segment (282) connecting the first segment (281) and the second bonding region (241) through the third via hole (2451); and the third wiring (270) is the first wiring (251), the fourth wiring (280) is the second wiring (261), the first driving integrated circuitry is the scanning driving integrated circuitry (250), and the second driving integrated circuitry is the data driving integrated circuitry (260); or the third wiring (270) is the second wiring (261), the fourth wiring (280) is the first wiring (251), the first driving integrated circuitry is the data driving integrated circuitry (260), and the second driving integrated circuitry is the scanning driving integrated circuitry (250).
  6. The display panel according to claim 1, wherein each repetition unit (246) comprises P first bonding electrodes and Q second bonding electrodes, and P and Q are each a positive integer.
  7. The display panel according to claim 1, wherein the first bonding region (210) comprises a plurality of second low level signal electrodes (294), Z signal transmission lines are arranged between two adjacent second low level signal electrodes (294), and the Z signal transmission lines comprise the first connection lines (220) and/or the second connection lines (230).
  8. The display panel according to claim 7, wherein the Z signal transmission lines comprise X first connection lines and Y second connection lines, and X and Y are each a positive integer.
  9. The display panel according to claim 1, wherein two scanning driving integrated circuitries (250) respectively arranged on two adjacent chip on films (240) are connected to each other via a scanning input/output signal line (310), and two data driving integrated circuitries (260) respectively arranged on two adjacent chip on films (240) are connected to each other via a data input/output signal line (320).
  10. A display device, comprising the display panel according to any one of claims 1 to 9.
  11. The display device according to claim 10, further comprising a power management integrated circuitry (510) and a timing sequence control circuitry (520), wherein the power management integrated circuitry (510) is configured to apply an operation voltage to the timing sequence control circuitry (520), the timing sequence control circuitry (520) is configured to apply a timing sequence signal to the chip on film (240), and the power management integrated circuitry (510) is further configured to apply a digital voltage signal and an analog voltage signal to the chip on film (240).
  12. A method for driving the display panel according to any one of claims 1 to 9, comprising: applying, by the scanning driving integrated circuitry (250) on the at least one chip on film (240), a gate scanning signal to each gate line (111) through the corresponding first wiring (251), the second bonding region (241), the first bonding region (210) and the corresponding first connection line (220) sequentially in a time division manner; and in the case that the gate scanning signal is applied to one gate line (111), applying, by the data driving integrated circuitry (260) on the at least one chip on film (240), a data signal to each data line through the corresponding second wiring (261), the second bonding region (241), the first bonding region (210) and the corresponding second connection line (230) sequentially.
  13. The method according to claim 12, wherein two scanning driving integrated circuitries (250) respectively arranged on two adjacent chip on films (240) are connected to each other via a scanning input/output signal line (310), and two data driving integrated circuitries respectively arranged on two adjacent chip on films (240) are connected to each other via a data input/output signal line (320), wherein the applying, by the scanning driving integrated circuitry (250) on the at least one chip on film (240), the gate scanning signal to each gate line (111) through the corresponding first wiring (251), the second bonding region (241), the first bonding region (210) and the corresponding first connection line (220) sequentially in a time division manner comprises: after a gate scanning signal has been applied by a scanning driving circuitry on a first chip on film (240) to a first gate line (111) through the corresponding first wiring (251), the second bonding region (241), the first bonding region (210) and the corresponding first connection line (220) sequentially in a time division manner, transmitting, by the first chip on film (240), a scanning on signal to a second chip on film (240) through the scanning input/output signal line (310), the first chip on film (240) and the second chip on film (240) being two adjacent chip on films (240), the first gate line (111) being a gate line (111) electrically connected to the scanning driving circuitry in the first chip on film (240); and after the second chip on film (240) has received the scanning on signal, applying, by a scanning driving circuitry in the second chip on film (240), a gate scanning signal to a second gate line (111) through the corresponding first wiring (251), the second bonding region (241), the first bonding region (210) and the corresponding first connection line (220) sequentially in a time division manner, the second gate line (111) being a gate line electrically connected to the scanning driving circuitry in the second chip on film (240), wherein the applying, by the data driving integrated circuitry (260) on the at least one chip on film (240), the data signal to each data line through the corresponding second wiring (261), the second bonding region (241), the first bonding region (210) and the corresponding second connection line (230) sequentially comprises: after the data signal has been applied by a data driving circuitry on a first chip on film (240) to a first data line through the corresponding second wiring (261), the second bonding region (241), the first bonding region (210) and the corresponding second connection line (230) sequentially, transmitting, by the first chip on film (240), a data on signal to a second chip on film (240) through the data input/output signal line (320), the first data line being a data line electrically connected to the data driving circuitry in the first chip on film (240); and after the second chip on film (240) has received the data on signal, applying, by a data driving circuitry in the second chip on film (240), a data signal to a second data line through the corresponding second wiring (261), the second bonding region (241), the first bonding region (210) and the corresponding second connection line (230) sequentially in a time division manner, the second data line being a data line electrically connected to the data driving circuitry in the second chip on film (240).

Description

TECHNICAL FIELD The present disclosure relates to the field of display technology, in particular to a display panel, a method for driving the display panel, and a display device. BACKGROUND Along with the continuous advancement of science and technology, people's pursuit of well appearance has become increasingly intense, and a narrow-bezel or even bezel-free display device has attracted more and more attention. In the related art, a driving integrated circuitry of the display device is intensively arranged on a side of a display region, so as to provide a narrow bezel on the other three sides of the display region. However, a width of a bezel on the side where the driving integrated circuitry is located increases, so it is impossible to provide the narrow-bezel display device as a whole or the bezel-free display device. US 2017/061857 A1 discloses a display apparatus including a display panel and a display panel driver. The display panel includes a first substrate and a second substrate facing the first substrate, wherein the first substrate includes a switching element, a data line and a gate line, wherein the data line and the gate line are electrically connected to the switching element. The display panel driver includes a data driving chip and a gate driving chip, wherein the data driving chip applies a data signal to the data line and the gate driving chip applies a gate signal to the gate line, wherein the gate driving chip is disposed on a surface of the data driving chip. US 2016/027398 A1 discloses a display apparatus including a display panel and a plurality of flexible printed circuit boards. The display panel includes a gate line and a data line. The plurality of flexible printed circuit boards is connected to one side of the display panel. Each of the plurality of flexible printed circuit board includes a gate driving chip configured to apply a gate signal to the gate line and a source driving chip configured to apply a data voltage to the data line. US 2008/024714 A1 discloses a multi-layer flexible film package which shields electromagnetic waves, prevents electrostatic discharge, and at the same time, performs a heat radiation function, and a liquid crystal display device having the same, include an insulating film having circuit patterns and internal ground wiring lines at a first side thereof, an insulating layer formed on the circuit patterns and the internal ground wiring lines, a driver integrated circuit ("IC") electrically connected to the circuit patterns and the internal ground wiring lines, a ground layer formed on a second side opposite the first side of the insulating film and connected to the internal ground wiring lines, and via holes formed through the insulating film and electrically connecting the internal ground wiring lines and the ground layer. JP 2014 228575 A discloses a liquid crystal display device capable of reducing uneven display generated in a scan line extending direction in a display screen of a large size and high precise display panel. The liquid crystal display device includes: a display panel having plural signal lines and plural scan lines; plural source drivers that generate a display gradation voltage based on an input display data input to the liquid crystal display device from the outside to supply the generated display gradation voltage to the plural signal lines; a gate driver that supplies a scan signal to the plural scan lines; and plural reference voltage generation circuits that generate plural reference voltages for generating the display gradation voltage. The plural reference voltages generated by the plural reference voltage generation circuits are different from each other in gradation scale. SUMMARY An object of the present disclosure is to provide a display panel, a method for driving the display panel, and a display device, so as to solve the above-mentioned problem. The invention is set out by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a display substrate in a display panel according to an embodiment of the present disclosure;Fig. 2 is a schematic view showing a chip on film in the display panel according to an embodiment of the present disclosure;Fig. 3 is another view showing the chip on film in the display panel according to an embodiment of the present disclosure;Fig. 4 is a schematic view showing wirings corresponding to Fig. 3;Fig. 5 is yet another schematic view showing the chip on film in the display panel according to an embodiment of the present disclosure;Fig. 6 is a schematic view showing wirings corresponding to Fig. 5;Fig. 7 is still yet another schematic view showing the chip on film in the display panel according to an embodiment of the present disclosure;Fig. 8 is a schematic view showing wirings corresponding to Fig. 7;Fig. 9 is still yet another schematic view showing the chip on film in the display panel according to an embodiment of the present disclosure;Fig. 10 is a sc