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EP-4012792-B1 - CAPACITORS WITH BUILT-IN ELECTRIC FIELDS

EP4012792B1EP 4012792 B1EP4012792 B1EP 4012792B1EP-4012792-B1

Inventors

  • CHANG, SOU-CHI
  • LIN, CHIA-CHING
  • OGUZ, Kaan
  • TUNG, I-CHENG
  • AVCI, UYGAR E.
  • METZ, Mathew
  • PENUMATCHA, Ashish Verma
  • YOUNG, IAN
  • SEN GUPTA, ARNAB

Dates

Publication Date
20260506
Application Date
20210903

Claims (8)

  1. An integrated circuit (IC) die, comprising: a capacitor, including: a top electrode region (102); a bottom electrode region (106); and a dielectric region (104) between and in contact with the top electrode region (102) and the bottom electrode region (106), wherein the dielectric region (104) includes a perovskite material, wherein the top electrode region (102) has a same material composition as the bottom electrode region (106), wherein the top electrode region (102) comprises a first material (108), said first material (108) comprising a metal with a face-centered cubic structure, and wherein the bottom electrode region (106) comprises a second material (110), characterized in that the top electrode region (102) has a different material structure than the bottom electrode region (104), and in that the second material (110) comprises the same metal as the first material (108) but with a hexagonal close-packed structure.
  2. The IC die of claim 1, wherein the top electrode region (102) includes germanium, lanthanum, hafnium, zirconium, yttrium, barium, lead, calcium, magnesium, beryllium, or lithium.
  3. The IC die of claim 2, wherein the top electrode region (102) has a thickness between 0.1 nanometers and 5 nanometers.
  4. The IC die of any of claims 2-3, wherein the top electrode region (102) is a first top electrode region, the capacitor further includes a second top electrode region, the first top electrode region is between the second top electrode region and the dielectric region (104), and the second top electrode region has a different material composition than the first top electrode region.
  5. The IC die of claim 4, wherein the second top electrode region includes ruthenium, iridium, copper, titanium and nitrogen, titanium, gold, platinum, silver, cobalt, molybdenum, or tungsten.
  6. The IC die of any of claims 4-5, wherein the second top electrode region has a thickness between 5 nanometers and 50 nanometers.
  7. The IC die of claim 1, wherein the top electrode region (102) has a different defect density than the bottom electrode region (106).
  8. The IC die of any preceding claim, wherein the capacitor is in a metallization stack of the IC die.

Description

Background Capacitors are used in many different electronic device designs. In some devices, for example, decoupling capacitors may be part of an integrated circuit (IC) die, a package substrate, and/or a circuit board. Kotru S et al. : "Electrical behavior of Pb0.95La0.05Zr0.54Ti0.46O3thin film based capacitors: Influence of space charge region", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS, vol. 124, no. 3, discusses the influence of the space charge region on the dielectric properties of Pt/PLZT/Pt ferroelectric capacitors. WO 2020/102416 A1 discloses a capacitive component with TiN/amorphous Al2O3/BiTiO3/ Pt/Si Substate structure. US2014183696A1 discloses methods to improve leakage for ZrO2 based high K MIM capacitors. Brief Description of the Drawings Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings. FIGS. 1-4 are side, cross-sectional views of example capacitors with built-in electric fields, in accordance with various embodiments.FIG. 5 is a top view of a wafer and dies that may include a capacitor in accordance with any of the embodiments disclosed herein.FIG. 6 is a side, cross-sectional view of an integrated circuit (IC) device that may include a capacitor in accordance with any of the embodiments disclosed herein.FIG. 7 is a side, cross-sectional view of an IC package that may include a capacitor in accordance with any of the embodiments disclosed herein.FIG. 8 is a side, cross-sectional view of an IC device assembly that may include a capacitor in accordance with any of the embodiments disclosed herein.FIG. 9 is a block diagram of an example electrical device that may include a capacitor in accordance with any of the embodiments disclosed herein. Detailed Description Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region. The capacitors disclosed herein may achieve a higher capacitance density than is achievable by conventional capacitors by including a built-in electric field across a polar dielectric (e.g., a perovskite oxide) to shift the maximum of the voltage-dependent capacitance density of polar dielectric capacitors to a target voltage range. In some embodiments, for example, the capacitors disclosed herein may achieve a capacitance density that is significantly greater than the capacitance density of existing capacitors in the absolute value voltage range between 0.5 volts and 1.9 volts. The capacitors disclosed herein may be fabricated under back-end processing conditions (e.g., at temperatures less than 400 degrees Celsius), and thus may be readily incorporated in a metallization stack of an integrated circuit (IC) die (e.g., as an on-die metal-insulator-metal (MIM) capacitor). In some embodiments, an on-die MIM capacitor in accordance with any of the embodiments disclosed herein may be used as a decoupling capacitor to stabilize the die's supply voltage (e.g., by mitigating voltage droop during load switching); such an on-die decoupling capacitor may be used in conjunction with an on-package decoupling capacitor and/or an on-board decoupling capacitor in an IC assembly, as discussed further below. In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the subject matter disclosed herein. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. For the purposes of the present disclosure, the phrases "A and/or B" and "A or B" mean (A), (B), or (A and B).