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EP-4020812-B1 - SEGMENTED DIGITAL-TO-ANALOG CONVERTER WITH SUBTRACTIVE DITHER

EP4020812B1EP 4020812 B1EP4020812 B1EP 4020812B1EP-4020812-B1

Inventors

  • CLARA, MARTIN
  • GRUBER, DANIEL
  • AZADET, KAMERAN

Dates

Publication Date
20260506
Application Date
20201223

Claims (15)

  1. A segmented digital-to-analog converter, DAC, comprising: at least two DAC segments (610,710,720) wherein each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment; at least one overrange DAC (620,730) configured to generate an analog output signal based on a control signal; and a dither control circuit (630,740) configured to add a dither to first input data supplied to a higher-order DAC segment, and subtract a portion of the dither by modifying second input data supplied to a lower-order DAC segment and generate the control signal for the overrange DAC (620,730) to subtract a remaining portion of the dither, wherein an output of the overrange DAC (620,730) is combined with an output of the segmented DAC (600,710,720) in an analog domain.
  2. The segmented DAC of claim 1, wherein the dither added to the first input data is one of +1, 0, and -1, or one of +1 and 0, or -1 and 0 and the portion of the dither subtracted from the second input data is a half of the dither added to the first input data.
  3. The segmented DAC of claim 1, wherein the dither added to the first input data is any integer in a range of +M to -M, or +M to 0, or -M to 0, M being a positive integer.
  4. The segmented DAC as in any one of claims 1-3, wherein the dither is added to every predetermined number of input samples to the segmented DAC.
  5. The segmented DAC as in any one of claims 1-4, wherein the higher-order DAC segment is thermometer-coded and the lower-order DAC segment is binary-coded.
  6. The segmented DAC as in any one of claims 1-5, wherein the dither is generated based on a pseudo-random sequence.
  7. The segmented DAC as in any one of claims 1-6, wherein the segmented DAC includes two DAC segments.
  8. The segmented DAC as in any one of claims 1-6, wherein the segmented DAC includes three DAC segments (1010, 1020, 1030), two dither control circuits (1060, 1070), and two overrange DACs (1040, 1050), wherein a first dither control circuit (1060) is configured to add a first dither to input data supplied to a first DAC segment (1010) and subtract a portion of the first dither from input data supplied to a second DAC segment (1020), and generate a first control signal for a first overrange DAC (1040) for subtracting a remaining portion of the first dither from an output of the segmented DAC in an analog domain, and a second dither control circuit (1070) is configured to add a second dither to the second input data supplied to the second DAC segment (1020) after subtracting the portion of the first dither from the second input data and subtract a portion of the second dither from a third input data supplied to a third DAC segment (1030), and generate a second control signal for a second overrange DAC (1050) for subtracting a remaining portion of the second dither from the output of the segmented DAC in an analog domain, or wherein the second dither control circuit (1070) is configured to add the second dither to the second input data supplied to the second DAC segment (1020) and subtract a portion of the second dither from the third input data supplied to the third DAC segment (1030) and generate the second control signal for the second overrange DAC for subtracting the remaining portion of the second dither from the output of the segmented DAC in an analog domain, and the first dither control circuit (1060) is configured to add the first dither to the first input data supplied to the first DAC segment (1010) and subtract a portion of the first dither from input data supplied to the second DAC segment (1020) after subtracting the portion of the second dither from the second input data, and generate the first control signal for the first overrange DAC (1040) for subtracting a remaining portion of the first dither from an output of the segmented DAC in an analog domain.
  9. The segmented DAC as in any one of claims 1-8, wherein the dither control circuit includes a delay unit for synchronizing outputs of the DAC segments and the overrange DAC.
  10. A method for digital-to-analog conversion using a segmented digital-to-analog converter, DAC, wherein the segmented DAC includes at least two DAC segments, and each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment, and the segmented DAC includes at least one overrange DAC configured to generate an analog output signal based on a control signal, the method comprising: receiving (1702) first input data at a higher-order DAC segment and receiving second input data at a lower-order DAC segment; adding (1704) a dither to the first input data supplied to the higher-order DAC segment; modifying (1706) the second input data supplied to the lower-order DAC segment to subtract a portion of the dither; and supplying (1708) a control signal to an overrange DAC to subtract a remaining portion of the dither, wherein the dither is compensated by the lower-order DAC segment and the overrange DAC, and an output of the overrange DAC is combined with an output of the segmented DAC in an analog domain.
  11. The method of claim 10, wherein the dither added to the first input data is one of +1, 0, and -1, or one of +1 and 0 or -1 and 0 and the portion of the dither subtracted from the second input data is a half of the dither added to the first input data.
  12. The method of claim 10, wherein the dither added to the first input data is any integer in a range of +M to -M, or +M to 0, or -M to 0, M being a positive integer.
  13. The method as in any one of claims 10-12, wherein the dither is added to every predetermined number of input samples to the segmented DAC.
  14. The method as in any one of claims 10-13, wherein the higher-order DAC segment is thermometer-coded and the lower-order DAC segment is binary-coded.
  15. A machine-readable storage including machine readable instructions, when executed, to implement a method as in any one of claims 10-14.

Description

Field Examples relate to a digital-to-analog converter (DAC), more particularly a segmented DAC with subtractive dither. Background A segmented DAC includes two or more segments of sub-DACs. In a segmented DAC, errors between different DAC segments (i.e. inter-segment errors) cause non-linear distortion. For large (close to full scale) narrowband signals, this error is often perceived as an increase in noise floor, while for broadband signals or heavily backed-off signals (narrowband and broadband), this class of errors tends to manifest itself as non-linear distortion at the converter output. Many modern communication systems (such as a cable modem, wireless base station transmitters, and the like) require a spectrally pure signal even in deep digital back-off. US 10,069,505 discloses that a dither is added to the digital input to the first DAC and converted to an analog output by the second DAC and subtracted from the output of the first DAC. US 10,069,505 discloses that the the first DAC includes an MSB section and an LSB section and the dither is subtracted from the output of the first DAC. JP H05 227026 discloses that a dither is added to a digital input to a DAC and the dither-added input data is converted to analog signal by the DAC and the dither is converted by a dither DAC and subtracted from the output of the DAC. Brief description of the Figures Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which FIG. 1 shows an example 2-segment DAC;FIG. 2 shows an example 3-segment DAC with two thermometer-coded upper segments and a binary-coded lowest segment;FIG. 3 shows spectrum of a single-tone signal with -0.35% MSB gain error in deep back-off;FIG. 4 shows static linearity characteristics of a 14 bit 3-segment DAC with -0.35% MSB gain error;FIG. 5 shows another example of a small, synthesized sine wave subject to inter-segment error in a 3-segment DAC;FIG. 6 is a schematic block diagram of a segmented DAC with subtractive dither partially in accordance with the invention as claimed;FIG. 7 shows an example 2-segment DAC with subtractive dither in accordance with the invention as claimed;FIG. 8 shows an example 2-segment DAC with the dither r[n] = {-1, 0, +1} and the scaling factor p = 0.5, using two overrange DAC cells of value 2B2- in accordance with the invention as claimed;FIG. 9 shows an example algorithm for digital processing to remove any residual correlation between the dither and the input data in case of 2-segment DAC of FIG. 8, in accordance with the invention as claimed;FIGS. 10 and 11 show an example 3-segment DAC with the dither r[n] = {-1, 0, +1} and the scaling factor p = 0.5 in accordance with the invention as claimed;FIG. 12 shows an example 2-segment DAC with single polarity dither, in accordance with the invention as claimed;FIG. 13 shows an example algorithm for digital processing to remove any residual correlation between the dither and the input data in case of 2-segment DAC, in accordance with the invention as claimed;FIG. 14 shows a 3-segment top-down implementation of single-polarity dither injection in accordance with the invention as claimed;FIG. 15 shows a single-tone spectrum with -0.35% MSB gain error and dither on;FIG. 16 shows spectrum of single-tone signal with 500fs MSB timing error and dithering activated;FIG. 17 is a flow diagram of a process for digital-to-analog conversion using a segmented DAC, partially in accordance with the invention as claimed;FIG. 18 illustrates a user device in which the examples disclosed herein may be implemented; andFIG. 19 illustrates a base station or infrastructure equipment radio head in which the examples disclosed herein may be implemented. Hereinafter, whenever an embodiment or an example is described, reference is to be made to the above figure list to determine whether the embodiment/example is to be read as covered by the claimed invention or as an embodiment/example which is not covered by the claimed invention. Detailed Description The invention is set out in the appended set of claims Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity. Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a simil