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EP-4020813-B1 - REFERENCE BUFFER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION AND MOBILE DEVICE

EP4020813B1EP 4020813 B1EP4020813 B1EP 4020813B1EP-4020813-B1

Inventors

  • GRUBER, DANIEL
  • LINDHOLM, CHRISTIAN
  • CLARA, MARTIN
  • CASCIO, GIACOMO

Dates

Publication Date
20260506
Application Date
20211126

Claims (15)

  1. An analog-to-digital converter, ADC, system (800), comprising: a biasing circuit (810) configured to supply a first bias signal (101) of a first polarity to a first signal line (830) and a second bias signal (102) of a second polarity to a second signal line (840); a plurality of sub-ADCs (820-M, 820-M+1, 820-M2) for digitizing an analog input signal, wherein the plurality of sub-ADCs (820-M, 820-M+1, 820-M2) are coupled to the first signal line (830) and the second signal line (840) for receiving the first bias signal (101) and the second bias signal (102), and wherein at least one of the plurality of sub-ADCs (820-M, 820-M+1, 820-M2) comprises, for coupling the at least one of the plurality of sub-ADCs (820-M, 820-M+1, 820-M+2) to the first signal line (830) and the second signal line (840), a reference buffer circuit (821-M) comprising: a first input node (110) configured to receive the first bias signal from the first signal line (830); a second input node (120) configured to receive the second bias signal from the second signal line (840); a first output node (130) configured to output a first reference signal (103) of the first polarity, wherein a first buffer amplifier (150) is coupled between the first input node (110) and the first output node (120); a second output node (140) configured to output a second reference signal (104) of the second polarity, wherein a second buffer amplifier (160) is coupled between the second input node (120) and the second output node (140); a first coupling path (170) comprising a first capacitive element (175), wherein the first coupling path (170) is coupled between the first output node (130) and the second input node (120); and a second coupling path (180) comprising a second capacitive element (185), wherein the second coupling path (180) is coupled between the second output node (140) and the first input node (110).
  2. The ADC system (800) of claim 1, wherein a capacitance of the first capacitive element (175) is equal to a capacitance of the second capacitive element (185).
  3. The ADC system (800) of or claim 1 or claim 2, wherein a respective capacitance of at least one of the first capacitive element (175) and the second capacitive element (185) is at minimum 50 % and at maximum 150 % of a gate-source capacitance of any transistor of the first buffer amplifier (150).
  4. The ADC system (800) of any one of claims 1 to 3, wherein the first coupling path (170) additionally comprises at least one of first resistive element and a first inductive element, and wherein the second coupling path (180) additionally comprises at least one of second resistive element and a second inductive element.
  5. The ADC system (800) of any one of claims 1 to 4, wherein a third coupling path (190) comprising a third capacitive element (195) is coupled between the first input node (110) and the second input node (120).
  6. The ADC system (800) of claim 5, wherein a capacitance of the third capacitive element (195) is equal to or greater than a gate-source capacitance of any transistor of the first buffer amplifier (150).
  7. The ADC system (800) of any one of claims 1 to 6, wherein the reference buffer circuit (821-M) further comprises a fourth capacitive element (196) coupled between the first input node (110) and a ground node.
  8. The ADC system (800) of claim 7, wherein a capacitance of the fourth capacitive element (196) is equal to or greater than a gate-source capacitance of any transistor of the first buffer amplifier (150).
  9. The ADC system (800) of any one of claims 1 to 8, wherein the reference buffer circuit (821-M) further comprises a fifth capacitive element (197) coupled between the second input node (120) and a ground node.
  10. The ADC system (800) of claim 9, wherein a capacitance of the fifth capacitive element (197) is equal to or greater than a gate-source capacitance of any transistor of the first buffer amplifier (150).
  11. The ADC system (800) of any one of claims 1 to 10, wherein at least one the first buffer amplifier (150) and the second buffer amplifier (160) is a source follower circuit.
  12. The ADC system (800) of any one of claims 1 to 11, wherein at least one the first buffer amplifier (150) and the second buffer amplifier (160) comprises cascaded source follower circuits.
  13. The ADC system (800) of any one of claims 1 to 12, wherein the at least one of the plurality of sub-ADCs (820-M, 820-M+1, 820-M2) further comprises: a first plurality of switches (822-M) for selectively coupling a first plurality of loads to the first output node (130) of the respective reference buffer; and a second plurality (823-M) of switches for selectively coupling a second plurality of loads to the second output node (140) of the respective reference buffer.
  14. The ADC system (800) of any one of claims 1 to 13, wherein the plurality of sub-ADCs (820-M, 820-M+1, 820-M2) are time-interleaved or pipelined.
  15. A receiver (1110, 1210), comprising: an analog-to-digital converter system (1120, 1220) according to any of claims 1 to 14; and analog circuitry (1130, 1230) configured to receive a receive signal, and to supply the analog input signal to the analog-to-digital converter system (1120, 1220) based on the receive signal.

Description

Field Examples relate to a reference buffering for Analog-to-Digital Converters (ADCs). In particular, examples relate to a reference buffer circuit for an ADC, an ADC system comprising the reference buffer circuit, a receiver comprising the ADC system, a base station comprising the receiver and a mobile device comprising the receiver. Background In ADCs such as time-interleaved ADCs or pipelined ADCs significant crosstalk can occur between the sub-ADC references. In some implementations every sub-ADC has its own reference buffer to allow for some isolation of reference voltages between the sub-ADCs. For example, document Lukas Kull et al.: "A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS", 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), IEEE, 10 November 2014 (2014-11-10), pages 89-92, XP032719813, DOI: 10.1 109/ASSCC.2014.7008867, ISBN: 978-1-4799-4090-5 propose such an ADC. One of the simplest buffer circuits is a source follower. A source follower structure is simple, small, power efficient and broadband due to low output impedance. Document Yuan Zhou et al.: "A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 54, no. 8, 1 August 2019 (2019-08-01), pages 2207-2218, XP011736154, ISSN: 0018-9200, DOI: 10.1109/JSSC.2019.2915583 proposed an ADC using source followers for the reference buffers. But source followers suffer from the effect that the gate-source capacitance couples the output of the buffer to the bias potential and resulting in kickback of the output to the bias lines. Document IPPEI AKITA ET AL: "A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier",SOLID STATE CIRCUITS CONFERENCE (A-SSCC), 2011 IEEE ASIAN, IEEE, 14 November 2011 (2011-11-14), pages 293-296, XP032090578,DOI: 10.1109/ ASSCC.2011.6123603ISBN: 978-1-4577-1784-0 also proposes an ADC using multiple reference buffers. Further, document US 2020/274545 A1 proposes an input buffer for a time-interleaved ADC with a differential source follower. The input buffer is for buffering an analog input signal to be digitized by the time-interleaved ADC. Capacitors couple between each input and its inverted output to cancel the parasitic capacitances between the gate and source terminals of the source followers. There may be a desire for improved reference buffering for ADCs. Brief description of the Figures Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which Fig. 1 illustrates a first example of a reference buffer circuit;Fig. 2 illustrates a comparison of exemplary bias and reference signals;Fig. 3 illustrates a second example of a reference buffer circuit;Fig. 4 illustrates a third example of a reference buffer circuit;Fig. 5 illustrates a fourth example of a reference buffer circuit;Fig. 6 illustrates a fifth example of a reference buffer circuit;Fig. 7 illustrates a sixth example of a reference buffer circuit;Fig. 8 illustrates an ADC system according to the invention as claimed.Fig. 9 illustrates a first exemplary comparison of reference voltages output by two buffer circuits;Fig. 10 illustrates a second exemplary comparison of reference voltages output by two buffer circuits;Fig. 11 illustrates an example of a base station; andFig. 12 illustrates an example of a mobile device. Detailed Description The invention is set out in the appended set of claims. Some examples are now described in more detail with reference to the enclosed figures However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of the features as well as alternatives to the features. Furthermore, the terminology used herein to describe certain examples should not be restrictive of further possible examples. Throughout the description of the figures same or similar reference numerals refer to same or similar elements and/or features, which may be identical or implemented in a modified form while providing the same or a similar function. The thickness of lines, layers and/or areas in the figures may also be exaggerated for clarification. When two elements A and B are combined using an "or", this is to be understood as disclosing all possible combinations, i.e. only A, only B as well as A and B, unless expressly defined otherwise in the individual case. As an alternative wording for the same combinations, "at least one of A and B" or "A and/or B" may be used. This applies equivalently to combinations of more than two elements. If a singular form, such as "a", "an" and "the" is used and the use of only a single element is not defined as mandatory either explicitly or implicitly, further examples may also use several elements to implement the same function. If a function is des