EP-4027376-B1 - VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES

EP4027376B1EP 4027376 B1EP4027376 B1EP 4027376B1EP-4027376-B1

Inventors

JEZEWSKI, CHRISTOPHER
LIN, KEVIN

Dates

Publication Date: 20260506
Application Date: 20210823

Claims (7)

An interconnect structure, comprising: a first plurality of interconnect lines (352, 332) of a first metallization layer formed above a semiconductor substrate (351); a second plurality of interconnect lines (356B) of a second metallization layer formed above the first metallization layer and extending in a first direction; a third plurality of interconnect lines (354A, 334) of a third metallization layer formed above the second metallization layer and extending in the first direction, wherein the second plurality of interconnect lines and the third plurality of interconnect lines are staggered such that individual interconnect lines of the third plurality of interconnect lines are laterally offset from individual interconnect lines of the second plurality of interconnect lines; and a via (356A, 336) coupling an individual interconnect line of the first plurality of interconnect lines to an individual interconnect line of the third plurality of interconnect lines, wherein the via (356A, 336) is a varied width via and has a lower portion (336A, 346A) in contact with the individual interconnect line of the first plurality of interconnect lines and an upper portion (336B, 346B) in contact with the individual interconnect line of the third plurality of interconnect lines, the upper portion having a greater width in the first direction than the lower portion; wherein the via is a barrier-less via in the sense that no barrier layer is intervening between the individual interconnect of the first plurality of interconnect lines and the via.
The interconnect structure of claim 1, further comprising a dielectric material adjacent to at least a portion of the individual interconnect lines of at least one of the first plurality of interconnect lines, the second plurality of interconnect lines and the third plurality of interconnect lines.
The interconnect structure of claim 1 or 2, further comprising air-gaps between the individual interconnect lines of the second plurality of interconnect lines.
The interconnect structure of claim 1 or 2, further comprising air-gaps between the individual interconnect lines of the third plurality of interconnect lines.
The interconnect structure of claim 1 or 2, wherein both the second plurality of interconnect lines and the third plurality of interconnect lines includes air-gaps between individual interconnect lines.
The interconnect structure of claim 1, 2, 3, 4 or 5, wherein the second plurality of interconnect lines and the third plurality of interconnect lines are at least partially surrounded by etch stop.
A system, comprising: a storage component; and an integrated circuit die coupled to the storage component, the integrated circuit die including an interconnect structure according to any of claims 1 to 6.

Description

TECHNICAL FIELD Embodiments of the disclosure pertain to staggered interconnect lines and, in particular, to via connections for staggered interconnect lines. BACKGROUND Low-k interlayer dielectrics (ILDs) and air gaps are used between structures in various interconnect technologies in order to reduce line-to-line capacitance as a means of improving overall performance. Interconnect structures that use low-k ILDs trade off improvements in line-to-line capacitance with reductions in patternability and mechanical stability and thus can be difficult to integrate. For copper layers, the use of air-gaps necessitates a moderate-k etch stop to hermetically seal the copper and prevent it from oxidizing. However, the etch stop material fills space between interconnect lines and reduces the overall capacitance benefit. US 6 392 299 B1 discloses an interconnect level that includes upper and lower partial levels having respective conductive lines offset heightwise from each other. SUMMARY Embodiments of the invention are set out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an interconnect structure according to a previous approach.FIG. 2A illustrates a staggered line interconnect structure according to an embodiment.FIG. 2B illustrates an interconnect structure that includes staggered lines and air-gaps in a staggered line according to an embodiment.FIG. 2C illustrates an interconnect structure that includes staggered lines with air-gaps in each of the staggered lines according to an embodiment.FIG. 3A illustrates via connections according to a previous approach.FIG. 3B illustrates via connections according to according to an embodiment.FIGS. 3C and 3D illustrate via connections according to according to an embodiment.FIGS. 4A-4K illustrate cross-sections of an interconnect structure at stages during the fabrication of the interconnect structure according to an embodiment.FIGS. 5A-5D illustrate cross-sections of an interconnect structure at stages during the fabrication of the interconnect structure according to an embodiment.FIG. 6 illustrates a cross-section of an interconnect structure according to an embodiment.FIGS. 7A-7L illustrate cross-sections of an interconnect structure at stages during the fabrication of the interconnect structure according to an embodiment.FIGS. 8A-8M illustrate different architectures of interconnect structures according to an embodiment.FIG. 9 illustrates a flowchart of a method for forming interconnect structures according to an embodiment.FIG. 10 illustrates a schematic of a computer system according to an embodiment.FIG. 11 illustrates an interposer that includes one or more implementations of the embodiments. DESCRIPTION OF THE EMBODIMENTS Via connections for staggered interconnect lines are described. It should be appreciated that although embodiments are described herein with reference to example staggered interconnect line implementations, the disclosure is more generally applicable to staggered interconnect line implementations as well as other type staggered interconnect lines implementations. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. The use of low-k interlayer dielectrics (ILDs) and air gaps between structures in interconnect technologies to reduce line-to-line and layer-to-layer capacitance in order to improve overall performance is a feature of previous approaches. Interconnect structures that use low-k ILDs trade off improvements in line-to-line capacitance with reductions in patternability and mechanical stability and are thus difficult to integrate. Air-gaps have been used in some products for 80nm and 160nm pitches. For copper lay