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EP-4052132-B1 - MEMORY BANK GROUP INTERLEAVING

EP4052132B1EP 4052132 B1EP4052132 B1EP 4052132B1EP-4052132-B1

Inventors

  • ARTIERI, ALAIN
  • LECLER, JEAN-JACQUES
  • THOZIYOOR, SHYAMKUMAR

Dates

Publication Date
20260506
Application Date
20201001

Claims (12)

  1. A method (1000) for memory bank interleaving in a synchronous dynamic random access memory, SDRAM, (102) system, comprising: generating (1002), by a memory controller (104), an initial physical memory address; generating, by the memory controller (104), new bank group address bits and new bank address bits by hashing a plurality of bank group address bits of the initial physical memory address, a plurality of bank address bits of the initial physical memory address, and a plurality of row address bits of the initial physical memory address; generating (1004) a modified physical memory address by replacing the bank group address bits and bank address bits of the initial physical memory address with the respective new bank group address bits and bank address bits; and providing (1006), by the memory controller (104), the modified physical memory address to an SDRAM (102) chip; and wherein the bank group address bits are in 11th and 12th bit positions of the initial and modified physical memory addresses, and the bank address bits are in 13th and 14th bit positions of the initial and modified physical memory addresses; or wherein the bank group address bits are in 7th and 11th bit positions of initial and modified physical memory addresses, and the bank address bits are in 13th and 14th bit positions of the initial and modified physical memory addresses.
  2. The method (1000) of claim 1, wherein hashing comprises applying a poly19 hash.
  3. The method (1000) of claim 1, wherein hashing comprises hashing the plurality of bank group address bits in combination with the plurality of bank address bits in combination with a rank address bit with the row address bits.
  4. The method (1000) of claim 3, wherein hashing comprises applying a poly37 hash.
  5. A method (1100) for memory bank interleaving in a synchronous dynamic random access memory, SDRAM, (102) system, comprising: generating (1102), by a memory controller (104), a physical memory address having a plurality of bank group address bits positioned nearer a least-significant bit, LSB, of the physical memory address than a most-significant bit, MSB, of the physical memory address, wherein a lower-order bit of the bank group address bits, BG[0], is mapped to a higher-order position in the physical address than a higher-order bit of the bank group address bits, BG[1], wherein the plurality of bank group address bits and the plurality of bank address bits span 11th through 14 bit positions of the physical memory address, wherein a 33rd bit position defines the MSB of the physical memory address; and providing (1104), by the memory controller (104), the physical memory address to an SDRAM (102) chip.
  6. The method (1100) of claim 5, wherein the physical memory address has the plurality of bank group address bits and a plurality of bank address bits positioned nearer the LSB of the physical memory address than the MSB of the physical memory address; or wherein bit positions of a lower-order bank group address bit and a higher-order bank group address bit are swapped; or wherein when the memory controller is operating in a write clock free-running mode a rank address bit is positioned nearer the LSB of the physical memory address than the MSB of the physical memory address.
  7. A system for memory bank interleaving in a synchronous dynamic random access memory, SDRAM, (102) system, comprising: a memory controller (104) configured to generate an initial physical memory address and to perform hashing upon a plurality of bank group address bits in combination with a plurality of bank address bits of the initial physical memory address and a plurality of row address bits of the initial physical memory address, the memory controller further configured to include a result of the hashing in a modified physical memory address in place of the plurality of bank group address bits and the plurality of bank address bits of the initial physical memory address; and wherein the memory controller (104) is further configured to provide the modified physical memory address to an SDRAM (102) chip; and wherein the bank group address bits are in 11th and 12th bit positions of the initial and modified physical memory addresses, and the bank address bits are in 13th and 14th bit positions of the initial and modified physical memory addresses; or wherein the bank group address bits are in 7th and 11th bit positions of the initial and modified physical memory addresses, and the bank address bits are in 13th and 14th bit positions of the initial and modified physical memory addresses.
  8. The system of claim 7, wherein hashing comprises applying a poly19 hash.
  9. The system of claim 7, wherein hashing comprises hashing the plurality of bank group address bits in combination with the plurality of bank address bits in combination with a rank address bit with the row address bits.
  10. The system of claim 7, wherein hashing comprises applying a poly37 hash.
  11. A system for memory bank interleaving in a synchronous dynamic random access memory, SDRAM, (102) system, comprising: a memory controller (104) configured to generate a physical memory address having one or more bank group address bits positioned nearer a least-significant bit ,LSB, of the physical memory address than a most-significant bit, MSB, of the physical memory address, wherein a lower-order bit of the bank group address bits, BG[0], is mapped to a higher-order position in the physical address than a higher-order bit of the bank group address bits, BG[1], wherein the plurality of bank group address bits and the plurality of bank address bits span 11th through 14 bit positions of the physical memory address, wherein a 33rd bit position defines the MSB of the physical memory address; and wherein the memory controller (104) is further configured to provide the physical memory address to an SDRAM (102) chip.
  12. The system of claim 11, wherein the physical memory address has the plurality of bank group address bits and a plurality of bank address bits positioned nearer the LSB of the physical memory address than the MSB of the physical memory address; or wherein bit positions of a lower-order bank group address bit and a higher-order bank group address bit are swapped; or wherein when the memory controller is operating in a write clock free-running mode a rank address bit is positioned nearer the LSB of the physical memory address than the MSB of the physical memory address.

Description

Portable computing devices ("PCDs") are becoming necessities for people on personal and professional levels. These devices may include cellular telephones (e.g., smartphones), portable digital assistants ("PDAs"), portable game consoles, palmtop computers, and other portable electronic devices. PCDs commonly contain integrated circuits or systems-on-a-chip ("SoCs") that include numerous components designed to work together to deliver functionality to a user. For example, an SoC may contain any number of processors, such as central processing units ("CPUs") with multiple cores, graphical processing units ("GPUs"), etc. Among other functions, such a processor may access memories. A common type of memory that an SoC processor may access is known as double data-rate synchronous dynamic random access memory ("DDR-SDRAM," or for brevity, "DDR"). As a PCD is a battery-powered device in which saving power is an important goal, a common type of DDR in PCDs is low-power DRR ("LPDDR"). The DDR technology, which includes LPDDR technology, has evolved in iterations commonly referred to as DDR, DDR2, DDR3, DDR4, DDR5, etc. A feature of some of the later DDR iterations, known as bank groups, organizes the memory into two or more bank groups, each having two or more banks. Two or more bank groups may be accessed in parallel. For example, in a DDR scheme having two bank groups, after issuing a command to access a first bank group, the memory controller may issue a command to access a second bank group before the first bank group access has completed. Issuing consecutive access commands directed in an alternating or ping-ponging manner between two bank groups results in lower latency than if two or more consecutive access commands were directed to the same bank group. US 2006/0236072 Al describes a memory controller that uses hashing of address bits-including row, bank, and group bits-to generate modified addresses, distributing memory accesses across different banks and groups in SDRAM to optimise performance for both sequential and strided access patterns. This prevents consecutive accesses to the same bank or group, improving bandwidth and reducing access delays. Extending the foregoing example to a DDR scheme having four bank groups, the memory controller may interleave access commands among the four bank groups in a manner that attempts to minimize instances in which two consecutive accesses are directed to the same bank group. More generally, to increase memory utilization the memory controller may interleave access commands among the four bank groups in a manner that attempts to spread accesses evenly across all bank groups and banks. It would be desirable to further improve spread among bank groups and banks and thus improve memory utilization and provide related benefits in DDR systems. SUMMARY OF THE DISCLOSURE Systems, methods and computer program products are disclosed for memory bank interleaving in a synchronous dynamic random access memory (SDRAM) system. An exemplary method for memory bank interleaving may include a memory controller generating new bank group address bits and new bank address bits by hashing a plurality of bank group address bits of an initial physical memory address, a plurality of bank address bits of the initial physical memory address, and a plurality of row address bits of the initial physical memory address. The method may further include the memory controller generating a modified physical memory address by replacing the bank group address bits and bank address bits of the initial physical memory address with the respective new bank group address bits and bank address bits. The method may include the memory controller providing the modified physical memory address to an SDRAM chip. Another exemplary method for memory bank interleaving may include a memory controller generating a physical memory address having a plurality of bank group address bits positioned nearer a least-significant bit (LSB) of the physical memory address than a most-significant bit (MSB) of the physical memory address. The method may include the memory controller providing the physical memory address to an SDRAM chip. BRIEF DESCRIPTION OF THE DRAWINGS In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as "102A" or "102B", the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures. FIG. 1 is a block diagram of a DDR-SDRAM system embodying systems and methods for interleaving memory bank groups, in accordance with exemplary embodiments.FIG. 2 illustrates application of a hashing method to a physical memory address scheme or mapping, in accordance with exemplary