Search

EP-4053830-B1 - PIXEL DRIVING CIRCUIT AND DRIVING METHOD THEREFOR, DISPLAY PANEL, AND DISPLAY DEVICE

EP4053830B1EP 4053830 B1EP4053830 B1EP 4053830B1EP-4053830-B1

Inventors

  • LIU, Dongni
  • XUAN, MINGHUA
  • CHEN, XIAOCHUAN
  • DONG, XUE
  • ZHENG, HAOLIANG
  • YUE, Han
  • CONG, Ning

Dates

Publication Date
20260506
Application Date
20200930

Claims (6)

  1. A display device, comprising a display panel, the display panel having a plurality of sub-pixel regions (P), the display panel including: a plurality of pixel driving circuits (1), a plurality of light-emitting diodes (D), each light-emitting diode (D) being connected to a corresponding pixel driving circuit (1), each pixel driving circuit (1) being disposed in a sub-pixel region (P) of the plurality of sub-pixel regions (P); a plurality of first scanning signal lines configured to provide first scanning signals to the plurality of pixel driving circuits (1), first scanning signal terminals (G1) connected to pixel driving circuits (1) in a same row of sub-pixel regions (P) being connected to a corresponding first scanning signal line; a plurality of second scanning signal lines configured to provide second scanning signals to the plurality of pixel driving circuits (1), second scanning signal terminals (G2) connected to pixel driving circuits (1) in a same row of sub-pixel regions (P) being connected to a corresponding second scanning signal line; a plurality of third scanning signal lines configured to provide third scanning signals to the plurality of pixel driving circuits (1), third scanning signal terminals (G3) connected to pixel driving circuits (1) in a same row of sub-pixel regions (P) being connected to a corresponding third scanning signal line, a plurality of enable signal lines configured to provide enable signals to the plurality of pixel driving circuits (1), enable signal terminals (EM) connected to pixel driving circuits (1) in a same row of sub-pixel regions (P) being connected to a corresponding enable signal line, and a plurality of first power supply voltage lines (VDDL) configured to provide first power supply voltage signals to the plurality of pixel driving circuits (1), first power supply voltage signal terminals (VDD) connected to pixel driving circuits (1) in a same column of sub-pixel regions (P) being connected to a corresponding first power supply voltage line (VDDL); the display panel further including: a plurality of first data lines configured to provide first data signals to the plurality of pixel driving circuits (1), first data signal terminals (Data1) connected to pixel driving circuits (1) in a same column of sub-pixel regions (P) being connected to a corresponding first data line; and a plurality of second data lines configured to provide second data signals to the plurality of pixel driving circuits (1), second data signal terminals (Data2) connected to pixel driving circuits (1) in a same column of sub-pixel regions (P) being connected to a corresponding second data line; or the display panel further including: a plurality of data lines configured to provide first data signals and second data signals to the plurality of pixel driving circuits (1), both first data signal terminals (G1) and second data signal terminals (G2) connected to pixel driving circuits (1) in a same column of sub-pixel regions (P) being connected to a corresponding data line, wherein each pixel driving circuit (1) includes a data writing sub-circuit (10), a driving sub-circuit (11), and a control sub-circuit (12); and the driving sub-circuit (11) includes a driving transistor (T1), wherein the data writing sub-circuit (10) is connected to a first scanning signal terminal (G1) of the first scanning signal terminals (G1), a second scanning signal terminal (G2) of the second scanning signal terminals (G2), a third scanning signal terminal (G3) of the third scanning signal terminals (G3), a first data signal terminal (Data1) of the first data signal terminals (Data1), a second data signal terminal (Data2) of the second data signal terminals (Data2), and the driving sub-circuit (11); and the data writing sub-circuit (10) is configured to: in response to a first scanning signal received from the first scanning signal terminal (G1) and a third scanning signal received from the third scanning signal terminal (G3), write a first data signal provided from the first data signal terminal (Data1) into the driving sub-circuit (11), and compensate for a threshold voltage of the driving transistor (T1); and in response to a second scanning signal received from the second scanning signal terminal (G2) and the third scanning signal received from the third scanning signal terminal (G3), write a second data signal provided from the second data signal terminal (Data2) into the driving sub-circuit (11), and compensate for the threshold voltage of the driving transistor (T1); the control sub-circuit (12) is connected to an enable signal terminal (EM) of the enable signal terminals (EM), a first power supply voltage signal terminal (VDD) of the first power supply voltage signal terminals (VDD), the driving sub-circuit (11), and an light-emitting diode (D); and the control sub-circuit (12) is configured to, in response to an enable signal received from the enable signal terminal (EM), connect the first power supply voltage signal terminal (VDD) to the driving transistor (T1), and connect the driving transistor (T1) to the light-emitting diode (D); the driving sub-circuit (11) is further connected to the first power supply voltage signal terminal (VDD); and the driving sub-circuit (11) is configured to: according to the first data signal and a first power supply voltage signal provided from the first power supply voltage signal terminal (VDD), output a driving signal to the light-emitting diode (D), so as to drive the light-emitting diode (D) to operate; and according to the second data signal and the first power supply voltage signal, control the light-emitting diode (D) to be in an operating state or in a non-operating state, wherein: the data writing sub-circuit (10) includes a first data writing sub-circuit (100) and a second data writing sub-circuit (101); the first data writing sub-circuit (100) is connected to the first scanning signal terminal (G1), the third scanning signal terminal (G3), the first data signal terminal (Data1), and the driving sub-circuit (11); and the first data writing sub-circuit (100) is configured to, in response to the first scanning signal and the third scanning signal that are received, write the first data signal into the driving sub-circuit (11), and compensate for the threshold voltage of the driving transistor (T1); and the second data writing sub-circuit (101) is connected to the second scanning signal terminal (G2), the third scanning signal terminal (G3), the second data signal terminal (Data2), and the driving sub-circuit (11); and the second data writing sub-circuit (101) is configured to, in response to the second scanning signal and the third scanning signal that are received, write the second data signal into the driving sub-circuit (11), and compensate for the threshold voltage of the driving transistor (T1), wherein the driving sub-circuit (11) further includes a capacitor (C1); the first data writing sub-circuit (100) includes a second transistor (T2) and a third transistor (T3); the second data writing sub-circuit (101) includes the third transistor (T3) and a fourth transistor (T4); the control sub-circuit (12) includes a fifth transistor (T5) and a sixth transistor (T6); a gate of the driving transistor (T1) is connected to a node (N1), a first electrode of the driving transistor (T1) is connected to a second electrode of the second transistor (T2), a second electrode of the fourth transistor (T4) and a second electrode of the fifth transistor (T5), and a second electrode of the driving transistor (T1) is connected to a first electrode of the third transistor (T3) and a first electrode of the sixth transistor (T6); one electrode of the capacitor (C1) is connected to the node (N1), and the other electrode of the capacitor (C1) is connected to the first power supply voltage signal terminal (VDD); a gate of the second transistor (T2) is connected to the first scanning signal terminal (G1), and a first electrode of the second transistor (T2) is connected to the first data signal terminal (Data1); a gate of the third transistor (T3) is connected to the third scanning signal terminal (G3), and a second electrode of the third transistor (T3) is connected to the node (N1); a gate of the fourth transistor (T4) is connected to the second scanning signal terminal (G2), and a first electrode of the fourth transistor (T4) is connected to the second data signal terminal (Data2); a gate of the fifth transistor (T5) is connected to the enable signal terminal (EM), and a first electrode of the fifth transistor (T5) is connected to the first power supply voltage signal terminal (VDD); and a gate of the sixth transistor (T6) is connected to the enable signal terminal (EM), and a second electrode of the sixth transistor (T6) is connected to a first electrode of the light-emitting diode (D).
  2. The display device according to claim 1, wherein the display panel further includes: a plurality of initial voltage signal lines (Vintl) configured to provide initial voltage signals to the plurality of pixel driving circuits (1), initial voltage signal terminals (Vint) connected to pixel driving circuits (1) in a same column of sub-pixel regions (P) being connected to a corresponding initial voltage signal line (Vintl), and a plurality of reset signal lines (RST) configured to provide first reset signals to the plurality of pixel driving circuits (1), first reset signal terminals (RST1) connected to pixel driving circuits (1) in a same row of sub-pixel regions (P) being connected to a corresponding reset signal line (RST), and the pixel driving circuit further includes a reset sub-circuit (13); the reset sub-circuit (13) is connected to a first reset signal terminal (RST1) of the first reset signal terminals (RST1), an initial voltage signal terminal (Vint) of the initial voltage signal terminals (Vint) and the driving sub-circuit (11); and the reset sub-circuit (13) is configured to, in response to a first reset signal received from the first reset signal terminal (RST1), transmit an initial voltage signal provided from the initial voltage signal terminal (Vint) to the driving sub-circuit (11).
  3. The display device according to claim 2, wherein the reset sub-circuit (13) includes a seventh transistor (T7); a gate of the seventh transistor (T7) is connected to the first reset signal terminal (RST1), a first electrode of the seventh transistor (T7) is connected to the initial voltage signal terminal (Vint), and a second electrode of the seventh transistor (T7) is connected to the driving sub-circuit (11).
  4. The display device according to claim 2, wherein the plurality of reset signal lines (RST) further configured to provide first reset signals to the plurality of pixel driving circuits (1), and second reset signal terminals (RST2) connected to pixel driving circuits (1) in a same row of sub-pixel regions (P) being connected to a corresponding reset signal line (RST), and the reset sub-circuit (13) is further connected to a second reset signal terminal (RST2) of the second reset signal terminals (RST2) and the light-emitting diode (D); and the reset sub-circuit (13) is further configured to, in response to a second reset signal received from the second reset signal terminal (RST2), transmit the initial voltage signal to the light-emitting diode (D); or the reset sub-circuit (13) is further connected to the second reset signal terminal (RST2); the reset sub-circuit (13) is configured to be connected to the light-emitting diode (D); and the reset sub-circuit (13) is further configured to, in response to the second reset signal received from the second reset signal terminal (RST2), transmit the initial voltage signal to the light-emitting diode (D); the reset sub-circuit (13) includes a seventh transistor (T7) and an eighth transistor (T8); a gate of the seventh transistor (T7) is connected to the first reset signal terminal (RST1), a first electrode of the seventh transistor (T7) is connected to the initial voltage signal terminal (Vint), and a second electrode of the seventh transistor (T7) is connected to the driving sub-circuit (11); and a gate of the eighth transistor (T8) is connected to the second reset signal terminal (RST2), a first electrode of the eighth transistor (T8) is connected to the initial voltage signal terminal (Vint), and a second electrode of the eighth transistor (T8) is connected to the light-emitting diode (D).
  5. A driving method for the display device according to any of claims 1 to 4, characterized in that : an image frame includes a first phase, a second phase, a third phase and a fourth phase, and the driving method comprises: in the first phase, in response to the first scanning signal and the third scanning signal that are received, writing (S1), by the data writing sub-circuit (10), the first data signal into the driving sub-circuit (11), and compensating (S1), by the data writing sub-circuit (10), for the threshold voltage of the driving transistor (T1), wherein the second transistor (T2) is turned on under control of the first scanning signal received from the first scanning signal terminal (G1), so that the first data signal provided from the first data signal terminal (Data1) is transmitted to the first electrode of the driving transistor (T1); and the third transistor (T3) is turned on under control of the third scanning signal received from the third scanning signal terminal (G3), so that the second electrode of the driving transistor (T1) and the gate of the driving transistor (T1) are short-circuited, and the first data signal and the threshold voltage of the driving transistor (T1) are written into the gate of the driving transistor (T1); in the second phase, in response to the enable signal that is received, connecting (S2), by the control sub-circuit (12), the driving transistor (T1) to the first power supply voltage signal terminal (VDD), and connecting (S2), by the control sub-circuit (12), the driving transistor (T1) to the light-emitting diode (D); and according to the first data signal and the first power supply voltage signal, outputting (S2), by the driving sub-circuit (11), the driving signal to the light-emitting diode (D), so as to drive the light-emitting diode (D) to operate, wherein the fifth transistor (T5) is turned on under control of the enable signal received from the enable signal terminal (EM), so that the first power supply voltage signal terminal (VDD) is connected to the first electrode of the driving transistor (T1), and the first power supply voltage signal provided from the first power supply voltage signal terminal (VDD) is transmitted to the first electrode of the driving transistor (T1); the sixth transistor (T6) is turned on under the control of the enable signal received from the enable signal terminal (EM), so that the second electrode of the driving transistor (T1) is connected to the first electrode of the light-emitting diode (D); and the driving transistor (T1) is turned on and outputs the driving signal to the light-emitting diode (D); in the third phase, in response to the second scanning signal and the third scanning signal that are received, writing (S3), by the data writing sub-circuit (10), the second data signal into the driving sub-circuit (11), and compensating (S3), by the data writing sub-circuit (10), for the threshold voltage of the driving transistor (T1), wherein the fourth transistor (T4) is turned on under control of the second scanning signal received from the second scanning signal terminal (G2), so that the second data signal provided from the second data signal terminal (Data2) is transmitted to the first electrode of the driving transistor (T1); and the third transistor (T3) is turned on under the control of the third scanning signal received from the third scanning signal terminal (G3), so that the second electrode of the driving transistor (T1) and the gate of the driving transistor (T1) are short-circuited, and the second data signal and the threshold voltage of the driving transistor (T1) are written into the gate of the driving transistor (T1); and in the fourth phase, in response to the enable signal that is received, connecting (S4), by the control sub-circuit (12), the driving transistor (T1) to the first power supply voltage signal terminal (VDD), and connecting (S4), by the control sub-circuit (12), the driving transistor (T1) to the light-emitting diode (D); and according to the second data signal and the first power supply voltage signal, controlling (S4), by the driving sub-circuit (11), the light-emitting diode (D) to be in the operating state or in the non-operating state, wherein the fifth transistor (T5) is turned on under the control of the enable signal received from the enable signal terminal (EM), so that the first power supply voltage signal terminal (VDD) is connected to the first electrode of the driving transistor (T1), and the first power supply voltage signal provided from the first power supply voltage signal terminal (VDD) is transmitted to the first electrode of the driving transistor (T1); the sixth transistor (T6) is turned on under the control of the enable signal received from the enable signal terminal (EM), so that the second electrode of the driving transistor (T1) is connected to the first electrode of the light-emitting diode (D); and the driving transistor (T1) is in an on state or in an off state according to the second data signal and the first power supply voltage signal, so that the light-emitting diode (D) is in the operating state or in the non-operating state accordingly.
  6. The driving method for the display device according to claim 5, wherein the pixel driving circuit (1) further includes a reset sub-circuit (13), and the reset sub-circuit (13) is connected to a first reset signal terminal (RST1), an initial voltage signal terminal (Vint), and the driving sub-circuit (11); and before the first phase, the driving method for the pixel driving circuit (1) further comprises: in a reset phase, in response to a first reset signal received from the first reset signal terminal (RST1), transmitting (S0), by the reset sub-circuit (13), an initial voltage signal provided from the initial voltage signal terminal (Vint) to the driving sub-circuit (11); or the pixel driving circuit (1) further includes the reset sub-circuit (13), and the reset sub-circuit (13) is connected to the first reset signal terminal (RST1), the initial voltage signal terminal (Vint), the driving sub-circuit (11), a second reset signal terminal (RST2) and the light-emitting diode (D); and before the first phase, the driving method for the pixel driving circuit (1) further comprises: in the reset phase, in response to the first reset signal received from the first reset signal terminal (RST1), transmitting (S0), by the reset sub-circuit (13), the initial voltage signal provided from the initial voltage signal terminal (Vint) to the driving sub-circuit (11); and in response to a second reset signal received from the second reset signal terminal (RST2), transmitting (S0), by the reset sub-circuit (13), the initial voltage signal to the light-emitting diode (D).

Description

This application claims priority to Chinese Patent Application No. 201911061511.3, filed on November 1, 2019. TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to a display device and a driving method therefore. BACKGROUND Compared to an organic light-emitting diode (OLED) display device, both a micro light-emitting diode (Micro LED) display device and a mini light-emitting diode (Mini LED) display device have a higher luminous efficiency and reliability, and a lower power consumption, which may become the mainstream of display products in the future. In both the Micro LED display device and the Mini LED display device, pixel driving circuits are used to drive LEDs to emit light, so as to realize display. Therefore, a structure of the pixel driving circuit is very important for ensuring the display effects of the Micro LED display device and the Mini LED display device. US2018240400A1 discloses a method for driving a pixel circuit. The method includes: a time for displaying a frame including N initialization phases and N data signal voltage writing phases before a light-emitting phase. The ith of the N data signal voltage writing phases is after the ith of the N initialization phases and before the (i+1)th of the N initialization phases, and the Nth data signal voltage writing phase is after the Nth initialization phase, 1≤i≤N-1, i is an integer and N is an integer greater than 1. In the initialization phase, an initialization voltage is applied to the gate electrode of the driving transistor by the initialization module. In the data signal voltage writing phase, a data signal voltage is applied to the gate electrode of the driving transistor by the data signal voltage writing module. US2016163267A1 discloses a pixel circuit and a display apparatus. The pixel circuit comprises three sub-pixel circuits (P1, P2, P3) and one power supply circuit (VL), wherein the three sub-pixel circuits (P1, P2, P3) share a data line (Data); the power supply circuit (VL) is connected to a first voltage level terminal (VA), a first signal control line (EM1) and the sub-pixel circuits (P1, P2, P3), and the power supply circuit (VL) is configured to supply a first voltage level to the sub-pixel circuits (P1, P2, P3) through the first voltage level terminal (VA) under the control of a signal of the first signal control line (EM1); and the sub-pixel circuits (P1, P2, P3) are connected to the power supply circuit (VL) and the data line (Data), and are configured to display a gray scale under the control of the first voltage level supplied by the power supply circuit (VL) and a data signal of the data line (Data). The pixel circuit can decrease the number of the signal lines used in the pixel circuit in the display apparatus, reduce the cost of the integrated circuit, and improve the pixel density of the display apparatus. US2015049125A1 discloses a pixel including a switching transistor connected to a data line, a first circuit to control compensation of a first driving transistor, and a second circuit to control compensation of a second driving transistor. The first and second circuits are connected to the switching transistor. The first and second transistors are connected to respective organic light emitting diodes of a same pixel. Compensation of the first and second driving transistors is based on respective first and second subscan signals, which overlap periods of corresponding common scan signals to be received by the switching transistor. US2015062195A1 discloses an electroluminescence display device including a controller which generates signals for controlling at least one pixel circuit during a first period and a second period. The controller controls current to a light-emitting element of the at least one pixel circuit based on a data voltage in the first period. The controller controls a supplying period of current to the light-emitting element based on a duty control voltage in the second period. SUMMARY In one aspect, the present invention provides a display device which is defined by appended claim 1. In another aspect, the present invention provides a driving method for the display device which is defined by appended claim 5. Further advantageous embodiments of the present disclosure are indicated in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to describe technical solutions in some embodiments of the present disclosure or the prior art more clearly, the accompanying drawings to be used in the description of some embodiments of the present disclosure or the prior art will be introduced below briefly. Obviously, the accompanying drawings to be described below are merely accompanying drawings of some embodiments of the present disclosure, and a person of ordinary skill in the art may obtain other drawings according to these drawings. In addition, the accompanying drawings to be described below may be regarded as schematic diagrams, but not li