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EP-4057149-B1 - A COMPUTER SYSTEM AND METHOD USING A FIRST PAGE TABLE AND A SECOND PAGE TABLE

EP4057149B1EP 4057149 B1EP4057149 B1EP 4057149B1EP-4057149-B1

Inventors

  • SMITH, CHRISTOPHER

Dates

Publication Date
20260506
Application Date
20220308

Claims (14)

  1. A computer system comprising: a physical memory (406) comprising: a first page table (412) comprising primary page table entries (502), wherein each page table entry among the primary page table entries is configured to store a mapping of a virtual memory address to a physical memory address and auxiliary information; and a second page table (414) comprising secondary page table entries (504) each storing at least one further auxiliary information, wherein each of the secondary page table entry corresponds to a respective primary page table entry in the first page table; and an address translation module (404) configured to, in response to receiving a request from a processor (402), walk through the first page table to identify a primary page table entry; characterised in that : the address translation module is further configured to, consecutive to identifying the primary page table entry, identify a location of the corresponding secondary page table entry among the secondary page table entries based on a location of the primary page table entry in the first page table, wherein each secondary page table entry is stored in the physical memory at a pre-determined offset from the corresponding primary page table entry.
  2. The computer system as claimed in claim 1, wherein the address translation module is further configured to retrieve the primary page table entry and the secondary page table entry.
  3. The computer system as claimed in claim 1, wherein the address translation module further copies the primary page table entry and the corresponding secondary page table entry retrieved into a cache (416).
  4. The computer system as claimed in any of the preceding claim, wherein the address translation module comprises a cache (416) configured to store a plurality of address translations, each from a virtual memory address to a physical memory address and optionally the cache is a translation look aside buffer, TLB.
  5. The computer system as claimed in claim 4, wherein the address translation module on receiving a request, that is a virtual address, is configured to: search, in the cache, for valid address translation from the virtual address to a physical address; provide the physical address to the processor, on identifying the valid address translation for the virtual address in the cache; and invoke a cache miss, in the absence of the valid address translation in the cache, wherein the invoking of the cache miss is handled by the address translation module by using a page table walker (418) or by raising a software exception handler.
  6. The computer system as claimed in claim 5, wherein the address translation module is adapted to walk through the first page table to identify the primary page table entry comprising a mapping of a physical address to the virtual address, on the occurrence of the cache miss.
  7. The computer system as claimed in any of the preceding claim, wherein the auxiliary information and the further auxiliary information comprises one or more memory attributes.
  8. The computer system as claimed in claim 1, wherein the address translation module is configured to calculate the location of the corresponding secondary page table entry using the pre-determined offset on identifying the valid primary page table entry in the first page table.
  9. The computer system as claimed in any of the preceding claim, wherein the second page table is stored in the physical memory at a location physically contiguous to the first page table or at a location not physically contiguous to the first page table.
  10. The computer system as claimed in any of the preceding claims, wherein the second page table is of a same size as the first page table, with primary and secondary page table entries having the same bit length, or the second page table is of a different size compared to the first page table, with secondary page table entries having a different bit length compared to the corresponding primary page table entries.
  11. The computer system as claimed in claim 10 when dependent upon claim 1, wherein the pre-determined offset is a predetermined fixed offset with each secondary page table entry being stored in the physical memory at a fixed same offset from the corresponding primary page table entries or the pre-determined offset is a predetermined variable offset with each secondary page table entry stored in the physical memory at a different offset from the corresponding primary page table entry.
  12. A computer implemented method performed by an address translation unit in a computer system, the computer system comprising a physical memory (406) comprising a first page table (412) comprising primary page table entries (502) wherein each page table entry among the primary page table entries is configured to store a mapping of a virtual memory address to a physical memory address and auxiliary information and a second page table (414) comprising secondary page table entries (504), each storing at least one further auxiliary information, wherein each of the secondary page table entries corresponds to a primary page table entry in the first page table, the computer implemented method comprising: receiving (702) a request from a processor (402); and walking (712) through the first page table to identify a primary page table entry; characterised in that the method further comprises: consecutive to identifying the primary page table entry identifying (714) a location of a corresponding secondary page table entry based on the location of primary page table entry in the first page table, wherein each secondary page table entry is stored in the physical memory at a pre-determined offset from the corresponding primary page table entry.
  13. The computer implemented method as claimed in claims 12, wherein the method further comprises retrieving (716, 708) the primary page table entry and the secondary page table entry.
  14. The computer implemented method as claimed in claims 12-13, wherein the method further comprises storing (716) a plurality of address translations, each from a virtual memory address to a physical memory address in a cache.

Description

TECHNICAL FIELD The present invention relates to address translation with page tables. BACKGROUND Memories store information for use in a computer system or computer hardware devices. Many computational tasks undertaken by a computer system require large amounts of memory and hence program code and data to be accessed by a processor are normally stored in a main memory (or physical memory) of the computer system. The main memory stores the program code and data in a plurality of locations within the main memory. Each memory location is addressable by a physical address which is an identifier of that location to the system. The identifier maybe thereafter used to access the corresponding memory location in the main memory when running a program or accessing a data. Today, with modern operating systems, computer systems are enabled to use the feature of virtual memory. Virtual memory is a concept of ideal abstraction of memory resources in the computer system. The main benefit of using virtual memory includes freeing applications from having to manage a shared memory space, increased security, and being able to conceptually use more memory than what might be physically available. The computer system comprises hardware units such as a memory management unit coupled to the processor performing memory translation from virtual address to physical address. A memory management unit uses a memory map such as a page table to hold the translation of virtual addresses seen by an application into physical addresses of the physical memory. Typically, the memory map stores the address translation and a plurality of memory attributes of the corresponding physical address accessed by the application. Memory attributes are characteristics of memory which are used to identify the way in which the memory works. Examples of the memory attributes include but are not limited to readability, writability, cacheability, shareability and the like. When independently developing a CPU architecture, it is possible to redefine the format of entries in the page table at will and hence newly desired memory attributes could be included in the page table. However, in some of the open standard instruction set architectures, it is not so easy to redefine the format of the entries in the page table. In such cases, the format of a page table provided by the standard may not provide all the features, in particular may not define all the necessary memory attributes, to allow more complex applications to operate as desired. US2020174945A1 relates to managing translation lookaside buffer entries based on associativity and page size, and discloses a system with a page table and two TLBs. US20140331023A1 discloses a virtual memory architecture that supports multiple attribute sets for two or more processing units. A first page table entry of the common page table may comprise a first set of attribute data for a first processing unit and data associated with an alternative location that include an attribute data for a second processing. Using the multiple sets of attribute data, the accessibility of a memory page for the two or more processing units may be managed individually. SUMMARY The invention is set out in the appended set of claims. The dependent claims set out particular embodiments. According to a first aspect there is provided a computer system according to claim 1. Each secondary page table entry is stored in the physical memory at a pre-determined offset from the corresponding primary page table entry. Optionally, the address translation module is further configured to retrieve the primary page table entry and the secondary page table entry. Optionally, the address translation module comprises the cache configured to store a plurality of address translations, each from a virtual memory address to a physical memory address and optionally the cache is a translation look aside buffer (TLB). Optionally, the address translation module on receiving a request, that is a virtual address, is configured to: search, in the cache, for valid address translation from the virtual address to a physical address; provide the physical address to the processor, on identifying the valid address translation for the virtual address in the cache; and invoke a cache miss, in the absence of the valid address translation in the cache. Optionally, the address translation module walks through the first page table to retrieve the primary page table entry comprising a mapping of a physical address to the virtual address, on the occurrence of the cache miss. Optionally, the auxiliary information and the further auxiliary information comprises one or more memory attributes. Optionally, the address translation module further copies the primary page table entry and the corresponding secondary page table entry retrieved into the cache. Optionally, the invoking of the cache miss is handled by the address translation module by using a page table walker. Optionally, the invokin