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EP-4057511-B1 - POWER AND SIGNAL-TO-NOISE RATIO REGULATION IN A VCO-ADC

EP4057511B1EP 4057511 B1EP4057511 B1EP 4057511B1EP-4057511-B1

Inventors

  • GARVI JIMENEZ-ORTIZ, RUBEN
  • HERNANDEZ-CORPORALES, LUIS
  • LOPEZ FERNANDEZ, GUILLERMO ALEJANDRO
  • PEREZ CRUZ, CARLOS ANDRES
  • Quintero Alonso, Andres

Dates

Publication Date
20260506
Application Date
20220308

Claims (13)

  1. A voltage-controlled oscillator analog-to-digital converter, VCO-ADC, (204, 300) comprising: a first source follower (SF) coupled between a first input terminal and a first internal node; a first VCO (304) having an input coupled to a second internal node; a first variable resistor (310) having a control signal input and coupled between the first internal node and the second internal node; and wherein the VCO (304), the variable resistor (310), and the source follower (SF) are connected in series to form a single current path, wherein a rest frequency of the VCO (304) is changed by the use of the variable resistor (310) in series with the source follower (SF), and a digital signal processing component (306) coupled between an output of the first VCO (304) and a output terminal (316).
  2. The VCO-ADC (204, 300) of claim 1 further comprising: a second source follower coupled between a second input terminal and a third internal node; a second VCO (308) having an input coupled to a fourth internal node and an output coupled to the digital signal processing component (306); and a second variable resistor (312) coupled between the third internal node and the fourth internal node.
  3. The VCO-ADC (204, 300) of any of the preceding claims, wherein the first variable resistor (310) comprises a plurality of switchable resistor components each having a control signal input.
  4. The VCO-ADC (204, 300) of any of the preceding claims, wherein the digital signal processing component (306) comprises a counter (402).
  5. The VCO-ADC (204, 300) of claim 1, wherein the source follower comprises an NMOS source follower and the variable resistor (310) comprises a plurality of resistor elements (312A, 312B, 312C) coupled to a plurality of PMOS transistors or to a plurality of transmission gates or to a plurality of NMOS transistors.
  6. The VCO-ADC (204, 300) of claim 5 or 1, wherein the source follower (SF) comprises a PMOS source follower and the variable resistor (310) comprises a plurality of resistor elements (312A, 312B, 312C) coupled to a plurality of NMOS transistors or to a plurality of transmission gates or to a plurality of PMOS transistors.
  7. A method of operating a voltage-controlled oscillator analog-to-digital converter (VCO-ADC) (204, 300) according to one of the claims 1 to 6, the method comprising: placing the VCO-ADC (204, 300) into a first operational mode by setting the variable resistor (310) to a first resistor value; and placing the VCO-ADC (204, 300) into a second operational mode by setting the variable resistor (310) to a second resistor value different from the first resistor value.
  8. The method of claim 7, wherein placing the VCO-ADC (204, 300) into a first operational mode comprises placing the VCO-ADC (204, 300) into a high power operational mode and wherein placing the VCO-ADC (204, 300) into a second operational mode comprises placing the VCO-ADC (204, 300) into a low power operational mode.
  9. The method of claim 7 or 8, wherein placing the VCO-ADC (204, 300) into a first operational mode comprises placing the VCO-ADC (204, 300) into a low quantization noise operational mode and wherein placing the VCO-ADC (204, 300) into a second operational mode comprises placing the VCO-ADC (204, 300) into a high quantization noise operational mode.
  10. The method of any of claims 7 to 9, wherein setting the variable resistor to a first resistor value comprises setting the variable resistor to a low resistor value and wherein setting the variable resistor (310) to a second resistor value comprises setting the variable resistor (310) to a high resistor value.
  11. The method of any of claims 7 to 10, wherein setting the variable resistor (310) to a first resistor value comprises programming a plurality of digital inputs of the variable resistor (310) to a first code and wherein setting the variable resistor (310) to a second resistor value comprises programming the plurality of digital inputs of the variable resistor (310) to a second code.
  12. The method of any of claims 7 to 11, further comprising placing the VCO-ADC (204, 300) into a third operational mode by setting the variable resistor (310) to a third resistor value different from the first resistor value and different from the second resistor value.
  13. The method of any of claims 7 to 12, wherein the VCO-ADC (204, 300) receives an analog input signal from a microelectromechanical system (MEMS) and provides a digital output signal corresponding to the analog input signal.

Description

TECHNICAL FIELD Embodiments of the present invention relate generally to a system and method of power and signal-to-noise ratio regulation in a voltage controlled oscillator analog-to-digital converter (VCO-ADC). BACKGROUND Currently many digital microphones available in the market are based on switched-capacitor sigma-delta analog-to-digital converter (ADC) implementations. In the switched-capacitor sigma-delta ADC technology, changes in quantization noise and power are accomplished by changing the frequency of a system clock. Different power modes can therefore be selected by changing the frequency of the system clock of the microphone integrated circuit. One issue associated with changing the frequency of the system clock is that, in order to avoid sound artefacts when changing between modes, a constant data rate is be kept at the output. But when the system clock frequency is changed, the sampling frequency is also changed. Digital interpolators having a variable interpolation function, in order to keep the constant data rate, are therefore sometimes used. The interpolator adds to the overall power consumption of the microphone and to the total silicon area of the microphone integrated circuit. Furthermore, care has to be taken to avoid the interpolator adding noise during transitions between different operational modes. The publication by G. Gielen et al.: Time Encoding Analog-to-Digital Converters: Bridging the analog gap to advanced digital CMOS -Part 2: Architectures and circuits", IEEE Solid State Circuits Magazine, vol. 12, no. 3, 25 August 2020, pages 18-27, XP055732015, USA, ISSN: 1943-0582, DOI:10.1109/ MSSC.2020.3002144 discloses a closed-loop, VCO-based architecture for sensor readout. The publication by G. Gielen et al.: Time Encoding Analog-to-Digital Converters: Bridging the analog gap to advanced digital CMOS - Part 1: Basis Principals", IEEE Solid State Circuits Magazine, vol. 12, no. 1, 1 April 2020, pages 47-55, XP011795104, USA, ISSN: 1943-0582, DOI:10.1109/MSSC.2020.2987536 discloses a VCO-based instrumentation system. SUMMARY According to an embodiment a voltage-controlled oscillator analog-to-digital converter (VCO-ADC) includes a first source follower coupled between a first input terminal and a first internal node; a first VCO having an input coupled to a second internal node; a first variable resistor having a control signal input and coupled between the first internal node and the second internal node; and wherein the VCO (304), the variable resistor (310), and the source follower (SF) are connected in series to form a single current path, wherein a rest frequency of the VCO (304) is changed by the use of the variable resistor (310) in series with the source follower (SF). A digital signal processing component is coupled between an output of the first VCO and a output terminal.. According to an embodiment a method of operating a voltage-controlled oscillator analog-to-digital converter (VCO-ADC) as described herein, the method includes placing the VCO-ADC into a first operational mode by setting the variable resistor to a first resistor value; and placing the VCO-ADC into a second operational mode by setting the variable resistor to a second resistor value different from the first resistor value. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of an exemplary switched capacitor sigma-delta ADC microphone implementation;Figure 2 is a block diagram of a VCO-ADC microphone implementation according to an embodiment;Figure 3 is a schematic diagram of a VCO-ADC having a variable resistor and source follower circuitry for controlling the operational mode of the microphone implementation shown in Figure 2, according to an embodiment;Figure 4 is a more detailed schematic of the VCO-ADC of Figure 3, according to an embodiment;Figure 5 is a schematic diagram of a VCO circuit having NMOS source followers and PMOS transistors for switching resistor elements, according to an embodiment;Figure 6 is a schematic diagram of a VCO circuit having NMOS source followers and transfer gates for switching resistor elements, according to an embodiment;Figure 7 is a schematic diagram of a VCO circuit having NMOS source followers and NMOS transistors for switching resistor elements, according to an exemplary circuit outside the scope of the present invention;Figure 8 is a schematic diagram of a VCO circuit having PMOS source followers and NMOS transistors for switching resistor elements, according to an embodiment;Figure 9 is a schematic diagram of a VCO circuit having PMOS source followers and transfer gates for switching resistor elements, according to an embodiment;Figure 10 is a schematic diagram of a VCO circuit having PMOS source followers and PMOS transistors for switching resistor ele