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EP-4063878-B1 - INTEGRATED CIRCUIT AND ASSOCIATED METHOD

EP4063878B1EP 4063878 B1EP4063878 B1EP 4063878B1EP-4063878-B1

Inventors

  • SALFELNER, ANTON

Dates

Publication Date
20260506
Application Date
20210325

Claims (12)

  1. An integrated circuit (300, 400) comprising: a first pad (302, 402) to be connected to an external terminal (318, 418) with a first bondwire (314, 414); a second pad (304, 404) to be connected to the external terminal (318, 418) with a second bondwire (316, 416); an active element (306, 406) having a node (308, 408) that is capacitively coupled to the first and second pads (302, 304, 402, 404), the node being associated with the external terminal (318, 418); a voltage or current source (310, 410) connected to the first pad (302, 402); and a detection module (312, 412) connected to the second pad (304, 404) and configured to determine an electrical continuity between the second pad (304, 404) and the first pad (302, 402), a first capacitor (340, 440) which is connected in series between the node (308, 408) of the active element (306, 406) and the first pad (302, 402) and between the node of the active element and the voltage or current source (310, 410) and a second capacitor (342, 442) which is connected in series between the node (308, 408) of the active element (306, 406) and the second pad (304, 404) and between the node of the active element and the detection module (312, 412) and wherein the first and second capacitors are configured to filter out the voltage or current supplied by the voltage or current source to the node of the active element.
  2. The integrated circuit of claim 1, comprising self-testing circuitry configured to: supply a voltage or current to the first pad using the voltage or current source; and determine the electrical continuity between the second pad and the first pad using the detection module.
  3. The integrated circuit of claim 2, wherein the voltage or current is a direct current, DC, voltage or current.
  4. The integrated circuit of any preceding claim, wherein the voltage or current source and/or the detection module comprises a low-pass filter circuit.
  5. The integrated circuit of any preceding claim, wherein the detection module is configured to determine the electrical continuity between the second pad and the first pad based on a measurement of the voltage or current at the second pad meeting a threshold.
  6. The integrated circuit of any preceding claim, comprising: at least one additional pad, in which each of the at least one additional pad is capacitively coupled to the node of the active element; and at least one additional detection module connected to a respective one of the at least one additional pad, in which each detection module is configured to determine an electrical continuity between the respective corresponding additional pad and the first pad.
  7. The integrated circuit of any preceding claim, comprising: a first electrostatic discharge, ESD, protection device (424) connected to the first pad; and a second ESD protection device (425) connected to the second pad;
  8. The integrated circuit of claim 7, wherein the first ESD device and the second ESD device comprise a common grounded-gate metal-oxide-semiconductor field-effect transistor, GGMOSFET.
  9. The integrated circuit of claim 7 or claim 8, comprising at least one additional ESD protection device, in which each additional ESD device is connected to a respective corresponding pad of the at least one additional pad.
  10. The integrated circuit of any preceding claim, in which the active element is a radio frequency, RF, receiver or transceiver, an ultra-wideband, UWB, transceiver or a Doherty amplifier.
  11. A packaged integrated circuit (301) comprising: the integrated circuit (300) of any preceding claim; the external terminal (318) associated with the node of the active element; the first bondwire (314) connecting the first pad (302) to the external terminal (318); and the second bondwire (316) connecting the second pad (304) to the external terminal (318).
  12. A method for testing an integrated circuit (300) having a first pad (302, 402) to be connected to an external terminal (318, 418) with a first bondwire (314, 414), a second pad (304, 404) to be connected to the external terminal (318, 418) with a second bondwire (316, 416), an active element (309) and a first and second capacitor (340, 440, 342, 442), the method comprising: supplying a voltage or current to the first pad; determining an electrical continuity between the first pad and the second pad, wherein the first pad and the second pad are capacitively coupled to a node (308) of the active element, the node being associated with the external terminal (318, 418), wherein the first capacitor (340, 440) is connected in series between the node (308, 408) of the active element (306, 406) and the first pad (302, 402) and between the node of the active element and the voltage or current source (310, 410), and wherein the second capacitor (342, 442) is connected in series between the node (308, 408) of the active element (306, 406) and the second pad (304, 404) and between the node of the active element and the detection module (312, 412) wherein the first and second capacitors are configured to filter out the voltage or current supplied by the voltage or current source to the node of the active element.

Description

Field The present disclosure relates to an integrated circuit and associated method, and in particular, although not exclusively, to testing integrated circuits for ultrawideband (UWB) transceivers. The present disclosure further relates to a packaged integrated circuit comprising such an integrated circuit. Background The RF performance of a packaged integrated circuit comprising a transceiver device can be enhanced by using multiple bondwires to connect the transceiver device to an RF pin. For example, circuit inductance and resistance may be reduced, and reliability may be increased by virtue of the multiple bondwires introducing redundancy into the packaged integrated circuit. Such an arrangement finds application in UWB applications, in which multiple bondwires may be provided at a single input or output in order to improve system performance. When multiple bondwires are used for a packaged integrated circuit, a problem may arise during fabrication that one bondwire (or, more generally, fewer than the total number of bondwires) has not bonded correctly. This cannot be readily detected during conventional testing for electrically connectivity since an electrical connection (which provides an electrical continuity) is provided by the at least one correctly bonded bondwire. For example, the connection may adequately pass a direct current or a more limited range of frequencies than required for the intended application. Nonetheless, the performance of the packaged integrated circuit may be sub-optimal when in operation in the field. JP 2009 147142 A relates to a semiconductor device for detecting bonding defects between pads and a common external terminal using an open detection circuit comprising some capacitors. US 2020/072891 A1 relates to a semiconductor device including a detection circuit that causes a predetermined current to flow through each of the connection lines connected to the two power supply potentials or the reference potential, amplifies the difference between the voltages of the two connection lines, and outputs the amplified difference. US 2010/045328 A1 relates to an integrated circuit including a detection circuit for detecting a bonding defect in a multi-bonding wire. US 2018/034404 A1 relates to a semiconductor device which is suited for detection of a fault of a bonding wire. Summary According to a first aspect of the present disclosure there is provided an integrated circuit as defined in claim 1. In one or more embodiments the integrated circuit comprises self-testing circuitry configured to: supply a voltage or current to the first pad using the voltage or current source; and determine the electrical continuity between the second pad and the first pad using the detection module. The voltage or current may be a direct current, DC, voltage or current. In one or more embodiments the voltage or current source and / or the detection module comprises a low-pass filter circuit. The low-pass filter circuit may be a resistor-capacitor, RC, filter circuit. In one or more embodiments the detection module is configured to determine the electrical continuity between the second pad and the first pad based on a measurement of the voltage or current at the second pad meeting a threshold. The level of the voltage or current at the second pad may substantially correspond to the voltage or current provided to the first pad by the voltage or current source. For example, the impedance of the first and second capacitors may be such that the voltage or current supplied by the voltage or current source is substantially blocked from reaching the node of the active element, or attenuated by at least one of 50%, 90%, 99%, 99.9%. The level of attenuation may be associated with a particular frequency, e.g. 0 Hz for a DC test signal. In one or more embodiments the integrated circuit comprises at least one additional pad, in which each of the at least one additional pad is capacitively coupled to the node of the active element. At least one additional detection module may be connected to a respective one of the at least one additional pad. Each detection module may be configured to determine an electrical continuity between the respective corresponding additional pad and the first pad. In one or more embodiments the integrated circuit comprises a first electrostatic discharge, ESD, protection device connected to the first pad. A second ESD protection device may be connected to the second pad. The first ESD device and the second ESD device may comprise a common grounded-gate metal-oxide-semiconductor field-effect transistor, GGMOSFET, and may be implemented as a GGNMOSFET. The integrated circuit may further comprise at least one additional ESD protection device. Each additional ESD device may be connected to a respective corresponding pad of the at least one additional pad. The first ESD device, the second ESD device and the at least one additional ESD protection device may comprise the common GGMOSFET. In one