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EP-4064544-B1 - ULTRA-WIDE-RANGE HIGH-POWER CONVERTER CIRCUIT

EP4064544B1EP 4064544 B1EP4064544 B1EP 4064544B1EP-4064544-B1

Inventors

  • LIU, HUI

Dates

Publication Date
20260506
Application Date
20210719

Claims (1)

  1. A converter circuit having high power in an ultra-wide range, comprising a first transformer module (210), a second transformer module (220), a first primary input module (110) which is arranged at a primary side of the first transformer module (210), a first secondary output module (310) which is arranged at a secondary side of the first transformer module (210), a second primary input module (120) which is arranged at a primary side of the second transformer module (220), a second secondary output module (320) which is arranged at a secondary side of the second transformer module (220), wherein the first primary input module (110) includes a first switch module (11) and a first LC module (13), the second primary input module (120) includes a second switch module (12) and a second LC module (14); wherein the first switch module (11) is connected with the first transformer module (210) through the first LC module (13), and the second switch module (12) is connected with the second transformer module (220) through the second LC module (14); the converter circuit having high power in an ultra-wide range further comprises a first output capacitor (Co1) and a second output capacitor (Co2), wherein the first output capacitor (Co1) is connected between two output terminals of a third rectification network (321), the second output capacitor (Co2) is connected between two output terminals of a fourth rectification network (322); a high and low voltage mode control module (400) operable to control the first output capacitor (Co1) and the second output capacitor (Co2) to be connected in series in a high-voltage mode and to be connected in parallel in a low-voltage mode, and a load output module (500), which is operable to receive a corresponding serial output voltage or a parallel output voltage, when the first output capacitor and the second output capacitor are connected in series or in parallel, respectively; wherein the first switch module (11) includes a first switch network (111) and a second switch network (112), the first LC module (13) includes a first LC network (113) and a second LC network (114), and the second switch module (12) includes a third switch network (121) and a fourth switch network (122), and the second LC module (14) includes a third LC network (123) and a fourth LC network (124); the first transformer module (210) includes at least a first transformer network (211) and a second transformer network (212); wherein the second transformer module (220) includes at least a third transformer network (221) and a fourth transformer network (222); wherein the first transformer network (211) comprises a first transformer (Ta1) and a second transformer (Ta2) wherein the primary windings of the first transformer (Ta1) and primary windings of the second transformer (Ta2) are connected in series; wherein the second transformer network (212) comprises a third transformer (Ta3) and a fourth transformer (Ta4) wherein the primary windings of third transformer (Ta3) and primary windings of the fourth transformer (Ta4) are connected in series; wherein the fourth transformer network (221) comprises a fifth transformer (Tb1) and a sixth transformer (Tb2) wherein the primary windings of the fifth transformer (Tb1) and primary windings of the sixth transformer (Tb2) are connected in series; wherein the fifth transformer network (222) comprises a seventh transformer (Tb3) and a eighth transformer (Tb4) wherein the primary windings of the seventh transformer (Tb3) and primary windings of the eighth transformer (Tb4) are connected in series; wherein the secondary windings of first and third transformers (Ta1 and Ta3) are connected in series, and the secondary windings of second and fourth transformers (Ta2 and Ta4) are connected in series; wherein the secondary windings of fifth and seventh transformers (Tb1 and Tb3) are connected in series, and the secondary windings of sixth and eighth transformers (Tb2 and Tb4) are connected in series; a first terminal of the first input capacitor (Cin1) is connected with a first terminal of the first switch network (111) and a first terminal of the second switch network (112); a second terminal of the first input capacitor (Cin1) is connected with a first terminal of the second input capacitor (Cin2), a second terminal of the second switch network (112), a first terminal of the third switch network (121), a first terminal of the fourth switch network (122) and a second terminal of the first switch network (111); a second terminal of the second input capacitor (Cin2) is connected with a second terminal of the third switch network (121) and a second terminal of the fourth switch network (122); a fourth terminal of the first switch network (111) is connected with the first transformer network (211) through the first LC network (113); a fourth terminal of the second switch network (112) is connected with the second transformer network (212) through the second LC network (114); a fourth terminal of the third switch network (121) is connected with the third transformer network (221) through the third LC network (123); a fourth terminal of the fourth switch network (122) is connected with the fourth transformer network (222) through the fourth LC network (124); the high and low voltage mode control module (400) includes a first switch (K1), a second switch (K2) and a third switch (K3), wherein the first switch (K1) is connected between a first terminal and a second terminal of the high and low voltage mode control module (400), and the second switch (K2) is connected between the first terminal of the high and low voltage mode control module (400) and a second terminal of the load output module (500), the third switch (K3) is connected between the second terminal of the high and low voltage mode control module (400) and a first terminal of the load output module (500); the first secondary output module (310) includes a first rectification network (311), a second rectification network (312) and a first parameter voltage equalization network (313); the second secondary output module (320) includes the third rectification network (321), the fourth rectification network (322) and a second parameter voltage equalization network (323) ; wherein the first secondary output module (310) or the second secondary output module (320) further includes a first resonant voltage equalization network (314) and a second resonant voltage equalization network (315); an input terminal of the first rectification network (311) is connected with the secondary side of the first transformer module (210), and an output terminal of the first rectification network (311) is connected with the fourth rectification network (322) through the first parameter voltage equalization network (313); an input terminal of the second rectification network (312) is connected with the secondary side of the first transformer module (210), and an output terminal of the second rectification network (312) is connected with the third rectification network (321) through the second parameter voltage equalization network (323), wherein the third rectification network (321) and the fourth rectification network (322) are also connected with the secondary side of the second transformer module (220); wherein the first resonant voltage equalization network (314) includes a first resonant voltage equalization unit (41) and a second resonant voltage equalization unit (42), and the second resonant voltage equalization network (315) includes a third resonant voltage equalization unit (43) and a fourth resonant voltage equalization unit (44); wherein the first parameter voltage equalization network (313) includes a first parameter voltage equalization unit (31) and a second parameter voltage equalization unit (32), and the second parameter voltage equalization network (323) includes a third parameter voltage equalization unit (33) and a fourth parameter voltage equalization unit (34); a first input terminal of the first rectification network (311) is connected with a secondary side of the first transformer network (211); a second input terminal of the first rectification network (311) is connected with a secondary side of the second transformer network (212); a first output terminal of the first rectification network (311) is connected with a first terminal of the third rectification network (321), a first terminal of the first parameter voltage equalization unit (31), a first terminal of the second parameter voltage equalization unit (32), a first terminal of the first resonant voltage equalization unit (41) and a first terminal of the second resonant voltage equalization unit (42); a second output terminal of the first rectification network (311) is connected with a fifth terminal of the third rectification network (321), a sixth terminal of the third rectification network (321), a second terminal of the first parameter voltage equalization unit (31), a second terminal of the second parameter voltage equalization unit (32), a second terminal of the first resonant voltage equalization unit (41) and a second terminal of the second resonant voltage equalization unit (42); wherein a first input terminal of the second rectification network (312) is connected with the secondary side of the first transformer network (211); a second input terminal of the second rectification network (312) is connected with the secondary side of the second transformer network (212); a first output terminal of the second rectification network (312) is connected with a first terminal of the fourth rectification network (322), a second terminal of the fourth rectification network, a first terminal of the third parameter voltage equalization unit (33), a first terminal of the fourth parameter voltage equalization unit (34), a first terminal of the third resonant voltage equalization unit (43), a first terminal of the fourth resonant voltage equalization unit, a second output terminal of the second rectification network (312) is connected with a fifth terminal of the fourth rectification network (322), a sixth terminal of the fourth rectification network (322), a second terminal of the third parameter voltage equalization unit (33) and a second terminal of the fourth parameter voltage equalization unit (34), a second terminal of the third resonant voltage equalization unit (43) and a second terminal of the fourth resonant voltage equalization unit; wherein a third terminal of the first parameter voltage equalization unit (31) is connected with a fourth terminal of the fourth rectification network (322); wherein a third terminal of the second parameter voltage equalization unit (32) is connected with a third terminal of the fourth rectification network (322); a third terminal of the third parameter voltage equalization unit (33) is connected with a third terminal of the third rectification network (321); a third terminal of the fourth parameter voltage equalization unit (34) is connected with a fourth terminal of the third rectification network (321); characterized in that: a third terminal of the first resonant voltage equalization unit (41) is connected with the first input terminal of the second rectification network (312); a third terminal of the second resonant voltage equalization unit (42) is connected with the second input terminal of the second rectification network (312); a third terminal of the third resonant voltage equalization unit (43) is connected with the second input terminal of the first rectification network (311); and a third terminal of the fourth resonant voltage equalization unit (44) is connected with the first input terminal of the first rectification network (311); wherein the first (41), second (42), third (43), and fourth (44) resonant voltage equalization units each include one serial diode voltage division branch and one LC resonant branch, wherein the serial diode voltage division branch includes a pair of serial diodes, and a central connection point of the pair of serial diodes is a voltage division point, the two terminals of the serial diode voltage division branch constitute the first terminal and the second terminal of each of the voltage equalization units (41, 42, 43, 44), and a first terminal of each of the LC resonant branch is connected with a voltage division point of each of the resonant voltage equalization units (41, 42, 43, 44), respectively, and a second terminal of each of the LC resonant branch forms the third terminal of the each of the resonant voltage equalization units (41, 42, 43, 44), respectively.

Description

TECHNICAL FIELD The disclosure relates to the technical field of power supply modules, and more particularly to a converter circuit having high power in an ultra-wide range. BACKGROUND In the field of high-power application, the input power source is three-phase AC power grid. Due to the power factor requirements, a three-phase active power factor correction circuit should be designed in the front stage. As the three-phase active power factor correction circuit receives the three-phase power grid input, it has a relatively high output bus voltage. Accordingly, the electrolytic capacitor is usually connected in series according to the current situation of the electron elements, as shown in FIG.1 . In the two-stage topology application of a charging power supply module, the output voltage BUS+ and BUS- of the front-stage circuit are used as the input voltage of the rear-stage DC/DC converter. Generally, as shown in FIGS.2A-2B, there are two different connection modes according to different requirements, which both have their own advantages and disadvantages. As shown in FIG.2A , the midpoint of DC input bus capacitor and the midpoint of power factor correction (PFC) output bus capacitor are connected together, so that the input bus capacitor of DC converter does not have the voltage equalization problem, however, the PFC output bus capacitor has a large voltage equalization pressure, which requires a voltage equalization control at the PFC side. At the same time, the high-frequency ripple of DC converter will enter the PFC output bus capacitor. As shown in FIG.2B, the midpoint of DC input bus capacitor and the midpoint of PFC output bus capacitor are separated by a resistor, so that PFC side is not affected by the DC side and the high-frequency ripple will not affect the PFC output bus capacitor. In order to take into account both the high voltage and the low voltage simultaneously and realize the constant power output in a wide voltage range, we have developed a wide range constant power converter, which can be used as the DC/DC converter shown in FIG.2A and FIG.2B , thus realizing a constant power charging for an electric automobile in an ultra-wide voltage range covering a low voltage of 250V to a high voltage of 1000V and a rapid charging for the electric automobile in different voltage levels. FIG.3 has shown the structural diagram of the wide range constant power converter. In the topology shown in FIG. 3 , circuit elements, especially resonant elements, such as resonant capacitor Lr, resonant capacitor Cr, transformer excitation inductor Lm and other resonant elements, have parameter deviations, which are usually in the range of 5% to 10%. In order to solve the voltage equalization problem caused by the deviations of circuit parameters in the topology, four voltage equalization networks are arranged at the secondary side of the transformer to solve the voltage equalization problem caused by the deviations of circuit parameters in the topology, so as to ensure the voltage equalization capacity of the primary capacitor and the secondary capacitor. In the later applications, we found that when the wide range constant power converter shown in FIG.3 is applied to the topology shown in FIG. 2A, it can operate normally. However, when the wide range constant power converter shown in FIG.3 is applied to the topology shown in FIG. 2B , it may face the problem of voltage equalization of the primary capacitors which are connected in series and the secondary capacitors which are connected in series, when carrying a light load or being started up with a light load. After long-term research and many experiments, we found that, the LLC resonant converter, under the common pulse frequency modulation (PFM) control manner, has the problem of non-monotonic gain when carrying a light load, thus resulting in an unstable output voltage. Therefore, in the light load condition, the PFM control manner should be changed. Different operator can adopt different control methods, such as phase-shift (for example, phase-shift full-bridge topology) control manner, pulse width modulation (PWM) control manner, burst control manner and so on. These control methods for the light load have their own advantages, which can solve the problem of PFM control manner, but may also bring other problems. For PWM or intermittent burst control manners, there will be no pulse generation for a period of time. In the case of no pulse generation, the parasitic parameters of the power tube and printed circuit board (PCB) will participate in the free resonance of the resonant capacitor Cr, resonant inductance Lr and transformer excitation inductance Lm. Under a specific input voltage, or a specific output voltage, when different light loads in different load forms (such as an inverter load, a CC mode, CV mode, CR mode of an electronic load-meter, etc.) are carried, in the specific dynamic process, it is found that the wide range constant power converter sh