Search

EP-4068261-B1 - DISPLAY DEVICE

EP4068261B1EP 4068261 B1EP4068261 B1EP 4068261B1EP-4068261-B1

Inventors

  • KIM, KEUNWOO

Dates

Publication Date
20260506
Application Date
20220316

Claims (11)

  1. A display device, comprising: a plurality of pixels (PX) each including: a first driving transistor (T1-1) including a first electrode connected to a first node (N1), a second electrode connected to a second node (N2), and a gate electrode connected to a third node (N3); a second driving transistor (T1-2) including a first electrode connected to a fourth node (N4), a second electrode connected to the first node (N1), a gate electrode connected to the third node (N3), and a lower gate electrode, to which the display device is configured to supply an emission control signal (EM); a second transistor (T2) including a first electrode configured to receive a data voltage (DATA), a second electrode connected to the first node (N1), and a gate electrode, to which the display device is configured to supply a write gate signal (GW); and a third transistor (T3) including a first electrode connected to the second node (N2), a second electrode connected to the third node (N3), and a gate electrode, to which the display device is configured to supply the write gate signal (GW), or a compensation gate signal (GC); wherein each of the pixels (PX) further includes: a fifth transistor (T5) including a first electrode, to which the display device is configured to supply a driving voltage (ELVDD), a second electrode connected to the fourth node (N4), and a gate electrode, to which the display device is configured to supply the emission control signal (EM); a sixth transistor (T6) including a first electrode connected to the second node (N2), a second electrode connected to a fifth node (N5), and a gate electrode, to which the display device is configured to supply the emission control signal (EM); a light emitting element (EL) including a first electrode connected to the fifth node (N5) and a second electrode, to which the display device is configured to supply a common voltage (ELVSS); the display device configured such that, in an emission period, the emission control signal (EM) of a gate-on level is applied to the gate electrode of the fifth transistor (T5) and the gate electrode of the sixth transistor (T6) to turn on the fifth transistor (T5) and the sixth transistor (T6), and the driving voltage (ELVDD) is applied to the fourth node (N4), and wherein, in the emission period, a threshold voltage of the second driving transistor (T1-2) is 0 volts.
  2. The display device of claim 1, configured such that, in a compensation period, the data voltage (DATA), is applied to the gate electrode of the first driving transistor (T1-1) along the second transistor (T2), the first driving transistor (T1-1), and the third transistor (T3) in response to the write gate signal (GW) or both the write gate signal (GW), and the compensation gate signal (GC).
  3. The display device of claim 2, wherein, in the compensation period, a threshold voltage of the first driving transistor (T1-1) is compensated.
  4. The display device of any preceding claim, wherein each of the pixels (PX) further includes: a fourth transistor (T4) including a first electrode, to which the display device is configured to supply a first initialization voltage (VINT), a second electrode connected to the third node (N3), and a gate electrode, to which the display device is configured to supply an initialization gate signal (GI).
  5. The display device of claim 4, configured such that, in an initialization period, the first initialization voltage (VINT) initializes the gate electrode of the first driving transistor (T1-1) and the gate electrode of the second driving transistor (T1-2) in response to the initialization gate signal (GI).
  6. The display device of claim 4 or 5, wherein each of the third transistor (T3) and the fourth transistor (T4) is an NMOS transistor.
  7. The display device of claim 4 or 5, wherein each of the third transistor (T3) and the fourth transistor (T4) is a PMOS transistor.
  8. The display device of claim 1, wherein the fifth transistor (T5) further includes a lower gate electrode, to which the display device is configured to supply the emission control signal (EM).
  9. The display device of any preceding claim, wherein each of the pixels (PX) further includes: a seventh transistor (T7) including a first electrode connected to the fifth node (N5), a second electrode, to which the display device is configured to supply a second initialization voltage (AINT), and a gate electrode, to which the display device is configured to supply a bypass gate signal (GB).
  10. The display device of claim 9, wherein each of the first driving transistor, (T1-1), the second driving transistor (T1-2), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) is a PMOS transistor.
  11. The display device of any preceding claim, wherein each of the pixels (PX) further includes: a storage capacitor (CST) including a first electrode connected to the third node (N3), and a second electrode, to which the display device is configured to supply the driving voltage (ELVDD).

Description

BACKGROUND 1. Field Embodiments relate to a display device, and more particularly, to a display device including a pixel having multiple driving transistors. 2. Description of the Related Art A display device may include a plurality of pixels. Each of the pixels may include a plurality of transistors, including a driving transistor, a capacitor, a light emitting element, or the like. When a channel of the driving transistor is short, an on-current of the driving transistor increases, so that the display device may be driven at a high speed. However, as a driving range of the driving transistor is narrowed when the channel of the driving transistor is short, grayscales expressed by the display device may be limited. As the driving range of the driving transistor is widened when the channel of the driving transistor is long, the display device may express various grayscales. However, as the on-current of the driving transistor decreases when the channel of the driving transistor is long, the driving speed of the display device may be limited. CN110992895A, US 2015/130691Al, CN108335672A, US2021/090494Al and US2021/049958Al discuss display devices. SUMMARY Embodiments provide a display device capable of high-speed driving and expression of various grayscales. In one aspect a display device is provided according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIG. 1 is a circuit diagram illustrating a pixel of a display device according to an embodiment.FIGS. 2, 3, and 4 are diagrams for explaining a driving of the pixel in FIG. 1.FIG. 5 is a plan view illustrating the pixel in FIG. 1.FIG. 6 is a plan view illustrating a lower pattern in FIG. 5.FIG. 7 is a plan view illustrating a first active layer in FIG. 5.FIG. 8 is a plan view illustrating a first conductive layer in FIG. 5.FIG. 9 is a plan view illustrating a second conductive layer in FIG. 5.FIG. 10 is a plan view illustrating a second active layer in FIG. 5.FIG. 11 is a plan view illustrating a third conductive layer in FIG. 5.FIG. 12 is a plan view illustrating a fourth conductive layer in FIG. 5.FIG. 13 is a plan view illustrating a fifth conductive layer in FIG. 5.FIG. 14 is a cross-sectional view illustrating the pixel taken along line I-I' in FIG. 5.FIG. 15 is a circuit diagram illustrating a pixel of a display device according to another embodiment.FIG. 16 is a plan view illustrating the pixel in FIG. 15.FIG. 17 is a plan view illustrating a lower pattern in FIG. 16.FIG. 18 is a cross-sectional view illustrating the pixel taken along line II-II' in FIG. 16.FIG. 19 is a circuit diagram illustrating a pixel of a display device according to an embodiment. DETAILED DESCRIPTION It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. It will be understood that, although the terms "first," "second," "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one," unless the content clearly indicates otherwise. "At least one" is not to be construed as limiting "a" or "an." "Or" means "and/or." As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation