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EP-4070452-B1 - CIRCUITS AND METHODS FOR MAINTAINING GAIN FOR A CONTINUOUS-TIME LINEAR EQUALIZER

EP4070452B1EP 4070452 B1EP4070452 B1EP 4070452B1EP-4070452-B1

Inventors

  • LI, MIAO
  • SUN, LI
  • LIU, HAO

Dates

Publication Date
20260513
Application Date
20201124

Claims (15)

  1. A receiver circuit comprising: an analog equalizer (400) including a first transistor (403) in series with a first resistor (406), a first current source (405) and a second transistor (413); a first bias circuit (300) configured to operate under similar process, voltage and temperature, PVT, conditions as the analog equalizer (400) to provide a first bias voltage (Vbias) to the first current source (405) and further configured to adjust a transconductance of the first transistor (403) to maintain a gain of the analog equalizer (400) constant over a range of process corners, operating voltages and operating temperatures; and a second bias circuit (500) configured to operate under similar PVT conditions as the analog equalizer (400) to provide a second bias voltage (Vbp) based on the first bias voltage (Vbias) to the second transistor (413) and further configured to adjust the resistance of the second transistor (413) to maintain a common mode voltage of the analog equalizer (400) constant over the range of process corners, operating voltages and operating temperatures.
  2. The receiver circuit of claim 1, wherein the first bias circuit comprises a third transistor (303), wherein a gate of the third transistor (303) is coupled to a reference voltage (Vref) and wherein a source of the third transistor (303) is coupled to a second current source (305) and wherein a drain of the third transistor (303) is coupled to a first input of a first operational amplifier (320) and wherein the third transistor (303) is a replica of the first transistor (403) and wherein a second input of the first operational amplifier is coupled to the reference voltage (Vref) and wherein an output of the first operational amplifier (320) is coupled to a gate of a fourth transistor (301) and to a gate of a fifth transistor (302) and wherein a source of the fourth transistor (301) is coupled to a supply voltage (Vdd) and a drain of the fourth transistor (301) is coupled to the drain of the third transistor (303) and wherein a source of the fifth transistor (302) is coupled to the supply voltage (Vdd) and a drain of the fifth transistor (302) is coupled to a drain of a sixth transistor (304) and to a first input of a second operational amplifier (321) and wherein a source of the sixth transistor (304) is coupled to a second resistor (306) and wherein a second input of the second operational amplifier (321) is coupled to the reference voltage (Vref) and wherein an output of the second operational amplifier provides a bias voltage (Vbias) to the second current source (305) and wherein the second current source is (305) is coupled in series with the second resistance (306) and with ground and wherein the second current source (305) is a replica of the first current source (405) and wherein the second resistor (306) is a replica of the first resistor (406).
  3. The receiver circuit of claim 2, wherein the gate of the third transistor (303) is coupled to an output of a bandgap voltage generator.
  4. The receiver circuit of claim 1, wherein the first transistor (403) includes a gate coupled to a data input from a transmission line, and wherein the first transistor (403) is disposed between the first resistor (406) and the first current source (405), and wherein the first current source (405) is disposed between the first transistor (403) and ground.
  5. The receiver circuit of claim 1, wherein the first transistor (403) and the first current source (405) are part of a first leg of a current mirror having a second leg, wherein the first leg is coupled to a first part of a differential data signal, and wherein the second leg is coupled to a second part of the differential data signal.
  6. The receiver circuit of claim 2, wherein first bias circuit (300) includes a current mirror, and wherein the third transistor (303) is disposed within a first leg of the current mirror and the fourth transistor (304) and the second resistor (306) are disposed within a second leg of the current mirror, further wherein the second current source (305) is disposed between the second resistor (306) and ground.
  7. The receiver circuit of claim 1, wherein the second bias circuit comprises a third operational amplifier (520), wherein a first input of third operational amplifier (520) is coupled to the reference voltage (Vref) and wherein a second input of the operational amplifier (520) is coupled to a gate of a seventh transistor (503) and wherein an output of the third operational amplifier (520) provides the second bias voltage (Vbp) to a gate of an eighth transistor (513) and wherein a source of the eighth transistor (513) is coupled to the voltage supply (Vdd) and wherein a drain of the eighth transistor (513) is coupled to a third resistor (506) and wherein the eighth transistor (513) is a replica of the second transistor (413) and wherein the third resistor (506) is coupled to a drain of the seventh transistor (503) and wherein the drain and the gate of the seventh transistor (503) are tied together (Vcom) and wherein a source of the seventh transistor (503) is coupled to a third current source (505) and wherein the seventh transistor (503) is a replica of the first transistor (403) and wherein the third current source (505) is coupled to ground and further receives the first bias voltage (Vbias) and wherein the third current source (505) is a replica of the first current source (405).
  8. The receiver circuit of claim 1, wherein the first bias circuit (300), the second bias circuit (500) and the equalizer circuit (400) are formed on a semiconductor chip.
  9. The receiver circuit of claim 8, wherein the semiconductor chip comprises a system on chip (210) having a multi-core processor configured to communicate with a memory chip (220) via the equalizer circuit.
  10. The receiver circuit of claim 8, wherein the semiconductor chip comprises a memory chip (220) configured to communicate with a system on chip (210) via the equalizer circuit.
  11. The receiver circuit of claim 8, wherein the semiconductor chip further comprises a deserializer (135) coupled to an output of the equalizer circuit (130, 400).
  12. A method for operating an equalizer circuit having a first current source (405) and a first transistor (413), the method comprising: at a first bias circuit (300), providing a first bias voltage to the first current source (405) to maintain a gain of the analog equalizer (400) constant over a range of process corners, operating voltages and operating temperatures; at a second bias circuit (500) providing a second bias voltage (Vbp) based on the first bias voltage (Vbias) to the first transistor (413) to maintain a common mode voltage of the analog equalizer (400) constant over the range of process corners, operating voltages and operating temperatures.
  13. The method of claim 12, further comprising: at a first bias circuit (300) having a second transistor (303) and a third transistor (304) arranged in separate legs of a current mirror, maintaining a drain voltage of the second transistor (303) and a drain voltage of the third transistor (304) equal to a gate voltage of the second transistor (303); generating a current by a second current source (305) in series with legs of the current mirror, wherein a gate voltage of the second current source (305) is provided by a first operational amplifier (321) disposed between a gate of the second transistor (303) and a drain of the third transistor (304); and applying the gate voltage as a first bias voltage (Vbias) to the first current source (405) within the equalizer circuit (400).
  14. The method of claim12, further comprising: maintaining a transconductance times resistance (gm*R) of the first bias circuit (300) constant over a range of process corners, operating voltages and operating temperatures; and maintaining a gm*R of the equalizer circuit (400) to be equal to the gm*R of the first bias circuit (300).
  15. The method of claim 12, wherein generating the second bias voltage (Vbp) includes maintaining a common mode voltage of the equalizer circuit (400) to be the same as a common mode voltage of the second bias circuit (500).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of U.S. Patent Application No. 17/099,183, filed November 16, 2020, and of U.S. Provisional Patent Application No. 62/944,817, filed December 6, 2019. TECHNICAL FIELD The present application relates, generally, to data receivers and, more specifically, to data receivers having analog equalizers. BACKGROUND Differential signal processing circuits, such as variable gain amplifiers (VGAs) and continuous time linear equalizers (CTLEs), receive and apply a particular frequency-dependent gain to an input differential signal to generate an output differential signal. The input differential signal is typically received at control terminals (e.g., gates) of input transistors (e.g., field effect transistors (FETs)), and the output differential signal are generated at other terminals (e.g., drains) of the input transistors. The effective direct current (DC) voltage level of a differential signal is generally referred to as the common mode voltage. The common mode voltage is generally the average voltage between the voltage levels of the positive and negative components of the differential signal. The common mode voltage affects the operating point of the devices to which the differential signal is applied. If the common mode voltage varies, the operating point of the devices varies, which may have undesirable consequences. In the context of a differential signal processing circuit, the input differential signal applied to the input transistors may have a common mode voltage that varies for a number of reasons. The gain applied to the input differential signal by the differential signal processing circuit results in an output differential signal that has a common mode voltage that varies with the common mode voltage of the input differential signal. In addition, process variation of the differential signal processing circuit itself may cause common mode voltage variation. As a result, the input transistors are subjected to varying common mode voltage levels, which has the adverse consequence of reducing gain and peaking control for the differential signal processing circuit. Additionally, the varying common mode voltage of the output differential signal may adversely affect the operation of one or more devices downstream of the differential signal processing circuit. Further reference is made to Talebbeydokhti et al. 2006, disclosing a method to generate stable transconductance (gm) M3 without using precise external components is The off-chip resistor in a conventional constant-gm bias circuit is replaced with a variable on-chip resistor. A MOSFET biased in triode region is used as a variable resistor. The resistance of the MOSFET is tuned by a background tuning scheme to achieve the stable transconductance that is immune to process, voltage and temperature variation. The transconductance generated by the constant-gm bias circuit designed in 0.18µm CMOS process with 1.5V supply displays less than 1% variation for a 20% change in power supply voltage and less than ±1.5% variation for a 60°C change in temperature. The whole circuit draws approximately 850µA from a 1.5V supply. Further reference is made to US 8 200 179 B1, disclosing a combined VGA-and-equalizer (VGA-EQ) circuit for a communication link including a current-mode logic ("CML") amplifier with an inductive load circuit. The CML amplifier has a gain control terminal and is operable to amplify, with an adjustable gain, a signal received at an input terminal and provide the amplified signal at an output terminal. The CML amplifier has a first gain at frequencies below a predetermined frequency value and a second gain at frequencies in a predetermined frequency range above the predetermined frequency value, wherein the second gain is higher than the first gain. The higher second gain of the VGA-EQ circuit causes a reduction in inter-symbol interference in a signal received by the receiver. Further reference is made to US 2009/224836 A1, disclosing a gain control system comprising a reference stage, a bias replication stage, an operational amplifier, an automatic gain control block, a gain stage, and a crystal oscillator. A negative feedback loop is formed by portions of the operational amplifier, the replica biasing stage, the gain stage, and the automatic gain control stage. The negative feedback loop operatively controls an amplitude of oscillation in the crystal oscillator. The automatic gain control block produces output currents at reference levels in proportion to an input current source. The output current reference levels provide a corresponding yet independent scaling of currents in the bias replication stage and the gain stage. By the scaling capabilities provided a high common mode of voltage is provided between the crystal oscillator and the voltage reference section while stable oscillating characteristics are provided over a broad frequency range. Further reference is