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EP-4070459-B1 - DAC WEIGHT CALIBRATION

EP4070459B1EP 4070459 B1EP4070459 B1EP 4070459B1EP-4070459-B1

Inventors

  • FREDRIKSSON, Henrik

Dates

Publication Date
20260513
Application Date
20191205

Claims (15)

  1. A method of weight calibration in a digital-to-analog converter, DAC, (25) the DAC (25) comprising an input port (100) for receiving a sequence of digital input words ( x [ n ]), each representing a digital input sample; a digital control circuit (110) configured to encode each digital input word ( x [ n ]) into a control word ( z [ n ]) representing the same digital input sample, each bit ( z i ) in the control word ( z [ n ]) having a corresponding bit weight ( w i ) and in the following considered to adopt values in {-1, 1}; a set (120) of analog weights, each associated with a unique one of the bits ( z i ) in the control word ( z [ n ]); summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word ( z i ) weighted by the respective associated analog weights; and an output (140) for outputting the analog sample; the method comprising, during a measurement procedure: for a first set of at least one bit of the control word ( z [ n ]), generating (300) the bits of the first set, such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero; for a second set of at least one bit of the control word ( z [ n ]), generating (310) the bits of the second set, such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero; for bits of the control word ( z [ n ]) that are not in the first set or the second set, if any, generating these bits such that the sum of these bits weighted by their respective bit weights is, on average, zero; and detecting (330) a DC level at the output of the DAC during the measurement procedure; and the method further comprising: adjusting (340) at least one analog weight in response to the detected DC level.
  2. The method according to claim 1, comprising for each bit of the the control word ( z [ n ]) not in the first set or the second set: generating (320) the bit such that the bit is, on average, zero.
  3. The method according to claim 1 or 2, wherein each of the first set and the second set consists of a single bit.
  4. The method according to claim 1 or 2, wherein the first set and the second set consist of different numbers of bits.
  5. The method according to any one of claims 1, 2, and 4, wherein each of the first set and the second set consists of multiple bits.
  6. A digital-to-analog converter, DAC, (25) comprising an input port (100) for receiving a sequence of digital input words ( x [ n ]), each representing a digital input sample; a digital control circuit (110) configured to encode each digital input word ( x [ n ]) into a control word ( z [ n ]) representing the same digital input sample, each bit ( z i ) in the control word ( z [ n ]) having a corresponding bit weight ( w i ) and in the following considered to adopt values in {-1, 1}; a set (120) of analog weights, each associated with a unique one of the bits ( z i ) in the control word ( z [ n ]); summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word ( z i ) weighted by the respective associated analog weights; and an output (140) for outputting the analog sample; wherein the digital control circuit (110), in at least one weight-calibration mode, is configured to: during a measurement procedure: for a first set of at least one bit of the control word ( z [ n ]), generate the bits of the first set such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero; for a second set of at least one bit of the control word ( z [ n ]), generate the bits of the second set such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero; and for bits of the control word ( z [ n ]) that are not in the first set or the second set, if any, generate these bits such that the sum of these bits weighted by their respective bit weights is, on average, zero; wherein the DAC (25) comprises: a DC-detection circuit (150) configured to detect a DC level at the output of the DAC (25) during the measurement procedure; and a calibration circuit (160) configured to adjust at least one analog weight in response to the detected DC level.
  7. The DAC (25) according to claim 6, wherein the digital control circuit (110) is configured to, in the at least one of the weight calibration modes, - for each bit of the control word ( z [ n ]) not in the first set or the second set: generate the bit such that the bit is, on average, zero.
  8. The DAC (25) according to claim 6 or 7, wherein, in at least one of the weight-calibration modes, each of the first set and the second set consists of a single bit.
  9. The DAC (25) according to any one of claims 6 to 8, wherein, in at least one of the weight-calibration modes, the first set and the second set consist of different numbers of bits.
  10. The DAC (25) according to any one of claims 6 to 9, wherein, in at least one of the weight-calibration modes, each of the first set and the second set consists of multiple bits.
  11. An electronic apparatus (1, 2) comprising the DAC according to any one of the claims 6 - 10.
  12. The electronic apparatus (1, 2) of claim 11, wherein the electronic apparatus is a communication apparatus.
  13. The electronic apparatus (1) of claim 12, wherein the communication apparatus is a wireless communication device for a cellular communications system.
  14. The electronic apparatus (2) of claim 12, wherein the communication apparatus is a base station for a cellular communications system.
  15. An integrated circuit (500) comprising the DAC (25) according to any one of the claims 6-10.

Description

Technical field The present invention relates to weight calibration in a digital-to-analog converter. Background Digital-to-analog converters (DACs) are interface circuits between the digital and the analog domain and are used whenever a conversion from a digital signal representation to an analog signal representation is needed. For instance, in radio transmitters, a lot of the signal processing is typically done in the digital domain. However, the signal to be fed into the antenna typically uses an analog representation. Hence, a DAC is used somewhere in the signal chain leading up to the antenna. Some types of DAC utilize analog weights that are selectively summed in the analog domain under control of a digital control word derived from the digital input of the DAC in order to generate the analog output of the DAC. Mismatch between nominal and actual values of the analog weights give rise to unwanted nonlinear distortion in the analog output of the DAC. This can be counteracted to some extent using so called dynamic element matching (DEM). DEM utilizes a redundant configuration where multiple different digital control words can be used to represent a given digital input value and randomizes between those different digital control words in order to alter the characteristics of the errors resulting from the mismatch. DEM does not remove the mismatch errors, but rather spreads the energy of the errors over a wider frequency range (than if no DEM had been applied). Other methods of mitigating the effect of weight mismatches include calibration. With this, distortion is not spread out but rater removed or subtracted from the output signal. Due to changes in physical properties (for example temperature changes, transistor aging, supply valuations etc) calibration typically needs to be performed in regular intervals. The traditional way of making calibration is to disrupt normal data through the DAC and send some form of known test pattern through the DAC and detect specific mismatch imperfections based on measurements of the output of the DAC. Other calibration methods include swapping parts of the DAC out of normal operations (swapping in extra parts instead) and calibrate critical propertied of the swapped-out part. These calibration methods either require disruption of DAC functionality during calibration or extra hardware to calibrate individual parts of the DAC at the same time performing normal operation. Both are disadvantageous from a performance and complexity point of view due to extra hardware in critical signal paths. US 9,991,900 B1 discloses a digital to analog converter that converts digital data in binary format to thermometer bit vectors. A first set of the thermometer bit vectors corresponds to most significant bits of the digital data and a second set of the thermometer bit vectors corresponds to least significant bits of the digital data. Connections of first current sources corresponding to the first set of the thermometer bit vectors and second current sources corresponding to the second set of the thermometer bit vectors are dynamically and randomly alternated to a first output line and a second output line. Calibration current is applied to the second current sources so a total current of the second current sources and the calibration current is within a predetermined range of an average current of the first current sources. US 2002/008651 A1 discloses a segmented digital-to-analog converter that includes: upper segments, a thermometer decoder, a randomizing circuit coupled between the thermometer decoder and the upper segments for randomizing an output of the thermometer decoder, a divider location selector circuit coupled between the randomizing circuit and the upper segments for choosing a selected segment from the upper segments, and lower segments coupled to the selected segment. Summary Embodiments of the present disclosure relates to detection of mismatch between analog weights in a DAC such that these mismatch errors can be reduced through calibration. Embodiments of the present disclosure are based on the inventor's insight that the mismatch between two analog weights, or two sets of analog weights, can be selectively detected as a DC offset at the output of the DAC provided that the generation of the digital control word follow certain criteria. Thereby, mismatch calibration of DACs is enabled without a need to interrupt normal operation or swapping parts of the DAC out of normal operation for offline calibration. According to a first aspect of the invention as claimed, a method of weight calibration in a DAC is provided. The DAC comprises an input port for receiving a sequence of digital input words, each representing a digital input sample, and a digital control circuit configured to encode each digital input word into a control word representing the same digital input sample. Each bit in the control word has a corresponding bit weight and is in the following considered to a