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EP-4071745-B1 - DISPLAY APPARATUS

EP4071745B1EP 4071745 B1EP4071745 B1EP 4071745B1EP-4071745-B1

Inventors

  • Kwak, Minchae
  • KIM, MIHAE
  • LEE, WANDO
  • CHO, SEUNGYEON
  • CHOI, JAEHO

Dates

Publication Date
20260513
Application Date
20220302

Claims (18)

  1. A display apparatus (10) comprising: a substrate (100) comprising a display area (DA) and a peripheral area (PA) outside the display area (DA); a first data line (DL1) extending from the display area (DA) into the peripheral area (PA); and a second data line (DL2) extending from the display area (DA) into the peripheral area (PA); wherein a 1-1 st lower load (LL1-1) located in the peripheral area (PA) and electrically connected to the first data line (DL1); a 1-2 nd lower load (LL1-2) located in the peripheral area (PA) and disposed on a same layer as the 1-1 st lower load (LL1-1) and electrically connected to the 1-1 st lower load (LL1-1); a 1-1 st upper load (UL1-1) located in the peripheral area (PA) and above the 1-1 st lower load (LL1-1), wherein the 1-1 st upper load (UL1-1) is insulated from the 1-1 st lower load (LL1-1); and a 1-2 nd upper load (UL1-2) located in the peripheral area (PA) and disposed on a same layer as the 1-1 st upper load (UL1-1) and above the 1-2 nd lower load (LL1-2), wherein the 1-2 nd upper load (UL1-2) is insulated from the 1-2 nd lower load (LL1-2) and electrically connected to the 1-1 st upper load (UL1-1); a lower load connection layer disposed on a first insulating layer covering the 1-1 st upper load (UL1-1) and the 1-2 nd upper load (UL1-2) and connected to the 1-1 st lower load (LL1-1) and the 1-2 nd lower load (LL1-2) via first contact holes; an upper load connection layer disposed on the first insulating layer covering the 1-1st upper load (UL1-1) and the 1-2nd upper load (UL1-2 and connected to the 1-1 st upper load (UL1-1) and the 1-2 nd upper load (UL1-2) via second contact holes; a 2-1 st lower load (LL2-1) located in the peripheral area (PA) and disposed on the same layer as the 1-1 st lower load (LL1-1) and electrically connected to the second data line (DL2); a 2-2 nd lower load (LL2-2) located in the peripheral area (PA) and disposed on the same layer as the 1-1 st lower load (LL1-1) and electrically connected to the 2-1 st lower load (LL2-1); a 2-1 st upper load (UL2-1) located in the peripheral area (PA) and disposed on the same layer as the 1-1 st upper load (UL1-1) and above the 2-1 st lower load (LL2-1), wherein the 2-1 st upper load (UL2-1) is insulated from the 2-1 st lower load (LL2-1); and a 2-2 nd upper load (UL2-2) located in the peripheral area (PA) and disposed on the same layer as the 1-1 st upper load (UL1-1) and above the 2-2 nd lower load (LL2-2), and electrically connected to the 2-1 st upper load (UL2-1), wherein the 2-2 nd upper load (UL2-2) is insulated from the 2-2 nd lower load (LL2-2); wherein a length of the first data line (DL1) is different than a length of the second data line (DL2), and wherein a first capacitance between lower loads including the 1-1 st lower load (LL1-1) and the 1-2 nd lower load (LL1-2) and upper loads including the 1-1 st upper load (UL1-1) and the 1-2 nd upper load (UL1-2) is greater than a second capacitance between lower loads including the 2-1 st lower load (LL2-1) and the 2-2 nd lower loads (LL2-2) and upper loads including the 2-1 st upper load (UL2-1) and the 2-2 nd upper load (UL2-2) such that the total capacitance of the first data line (DL1) is equal to the total capacitance of the second data line (DL2).
  2. The display apparatus (10) of claim 1, wherein, when viewed from a direction perpendicular to the substrate (100), the 1-1 st upper load (UL1-1) overlaps the 1-1 st lower load (LL1-1), and the 1-2 nd upper load (UL1-2) overlaps the 1-2 nd lower load (LL1-2). .
  3. The display apparatus (10) of at least one of claims 1 to 2, wherein a distance from the first data line (DL1) to a center of the display area (DA) is greater than a distance from the second data line (DL2) to the center of the display area (DA).
  4. The display apparatus (10) of at least one of claims 1 to 3, further comprising: a thin-film transistor located in the display area (DA), electrically connected to a display element, and including a gate electrode, wherein the 1-1 st lower load (LL1-1), the 1-2 nd lower load (LL1-2), and the gate electrode have a same layer structure.
  5. The display apparatus (10) of claim 4, wherein the 1-1 st lower load (LL1-1), the 1-2 nd lower load (LL1-2), and the gate electrode are on a same layer.
  6. The display apparatus (10) of at least one of claims 4 to 5, further comprising: a capacitor electrode of a storage capacitor located in the display area (DA) and above the gate electrode, wherein the 1-1 st upper load (UL1-1), the 1-2 nd upper load (UL1-2), and the capacitor electrode have a same layer structure.
  7. The display apparatus (10) of claim 6, wherein the 1-1 st upper load (UL1-1), the 1-2 nd upper load (UL1-2), and the capacitor electrode are on a same layer.
  8. The display apparatus (10) of claim 1, further comprising: a first scan connection line which is disposed on a second insulating layer covering the lower load connection layer and the upper load connection layer, and extends from a scan driving circuit located in the peripheral area (PA) to cross over the lower load connection layer and the upper load connection layer; a second scan connection line which is disposed on the first insulating layer, and has a first end electrically connected to the first scan connection line through a third contact hole defined in the second insulating layer; and a scan line electrically connected to a second end of the second scan connection line opposite the first end.
  9. The display apparatus (10) of claim 8, wherein the first data line (DL1) is disposed on the second insulating layer.
  10. The display apparatus (10) of at least one of claims 8 to 9, further comprising: a test line disposed on the second insulating layer in the peripheral area (PA) and including a portion parallel to a portion of the first scan connection line.
  11. The display apparatus (10) of claim 10, wherein the test line and the first data line (DL1) are integrally formed as a single body.
  12. The display apparatus (10) of at least one of claims 10 to 11, wherein the test line is electrically connected to a lighting test circuit located in the peripheral area (PA).
  13. The display apparatus (10) of at least one of claims 8 to 12, further comprising: a power line disposed on the second insulating layer, extending from the display area (DA) into the peripheral area (PA), and electrically connected to the 1-1 st upper load (UL1-1).
  14. The display apparatus (10) of claim 13, wherein the power line is parallel to the first data line (DL1) in the display area (DA).
  15. The display apparatus (10) of claim 1, further comprising: a first emission connection line which is disposed on a second insulating layer covering the lower load connection layer and the upper load connection layer, and extends from a scan driving circuit located in the peripheral area (PA) to cross over the lower load connection layer and the upper load connection layer; a second emission connection line which is disposed on the first insulating layer, and has a first end electrically connected to the first emission connection line through a fourth contact hole defined in the second insulating layer; and an emission control line extending into the display area (DA) and electrically connected to a second end of the second emission connection line opposite the first end.
  16. The display apparatus (10) of claim 15, wherein the emission control line, the 1-1 st upper load (UL1-1), and the 1-2 nd upper load (UL1-2) are on a same layer.
  17. The display apparatus (10) of at least one of claims 1 to 16, wherein, when viewed from a direction perpendicular to the substrate (100), a central axis passing through a center of the 1-1 st lower load (LL1-1) and a central axis passing through a center of the 1-2 nd lower load (LL1-2) are located on a same imaginary straight line, and a direction in which the first data line (DL1) extends in the display area (DA) is parallel to the imaginary straight line.
  18. The display apparatus (10) of at least one of claims 1 to 17, wherein, when viewed from a direction perpendicular to the substrate (100), the contour of the display area (DA) is free of peaks and/or has a circular or an elliptical shape.

Description

BACKGROUND 1. Field The present invention relates to a display apparatus, and more particularly, to a display apparatus for which a defect ratio in a manufacturing process is reduced. 2. Description of the Related Art US 2021/036087 A1 describes a display apparatus including a plurality of pixel circuits at a display area, the display area having a non-quadrangular shape, a first signal line extending on the display area in a first direction, and electrically connected to a first pixel circuit from among the plurality of pixel circuits, a first voltage line extending on the display area in the first direction, a first load compensation capacitor adjacent to an end portion of the first signal line and an end portion of the first voltage line, a test circuit outside the display area, an output line electrically connected to the test circuit, and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other. US 2019/019789 A1 improves display quality in non-rectangular configurations by reducing defects caused by static electricity, which is accomplished by patterning and dividing the conductive layers within load matching parts to reduce the charge area. US 2018/204889 A1 compensates varying gate line capacitive loads using either gate signal adjustments or supplemental loading structures like capacitors or dummy pixels. A display apparatus typically includes various lines to control whether to perform light emission from display elements arranged in a display area or a level of the light emission. For example, the display apparatus may include a data line to control a degree of light emission of a display apparatus according to an electrical signal received via the data line. SUMMARY However, defects may occur in a manufacturing process of the display apparatus according to the related art. It is the object of the present invention to provide a display apparatus, a defect ratio of which in a manufacturing process is reduced. The term "defect ratio" is to be understood as "frequency" or "number" of defects. This object is achieved by the subject matter of independent claim 1. Preferred embodiments are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a schematic plan view of a portion of a display apparatus according to an embodiment;FIG. 2 is an equivalent circuit diagram of a pixel included in the display apparatus of FIG. 1;FIG. 3 is a conceptual diagram illustrating an enlarged region A of the display apparatus of FIG. 1;FIG. 4 is a conceptual diagram illustrating an enlarged region B of the display apparatus of FIG. 3;FIG. 5 is a schematic cross-sectional view of portions of the display apparatus of FIG. 4;FIG. 6 is a conceptual diagram of an enlarged portion of a display apparatus according to another embodiment; andFIG. 7 is a conceptual diagram illustrating an enlarged region B of the display apparatus of FIG. 6. DETAILED DESCRIPTION Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, where like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one," unless the content clearly indicates otherwise. "At least one" is not to be construed as limiting "a" or "an." "Or" means "and/or." As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b or c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. As the present disclosure allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. The effects and