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EP-4080565-B1 - SEMICONDUCTOR DEVICE

EP4080565B1EP 4080565 B1EP4080565 B1EP 4080565B1EP-4080565-B1

Inventors

  • TAKEDA, SHUN

Dates

Publication Date
20260513
Application Date
20220309

Claims (11)

  1. A semiconductor device (100) comprising: a first substrate (11); a first metal layer (21) disposed on the first substrate (11); a second metal layer (22) disposed on the first substrate (11) and spaced apart from the first metal layer (21); a second substrate (12) spaced apart from the first substrate (11) in a first direction, and including a main wiring (61, 62, 63, 64) and a signal wiring (66, 67); a plurality of first semiconductor elements (30) disposed on the first metal layer (21); a plurality of second semiconductor elements (31) disposed on the second metal layer (22); a first terminal (51); a second terminal (52); a third terminal (53) electrically connected to the second metal layer (22); first and second gate terminals (54, 55); a first source sense terminal (56); and a second source sense terminal (57), the main wiring comprising: a first wiring layer (61) electrically connected to the first metal layer (21) and the first terminal (51); a second wiring layer (62) electrically connected to the second metal layer (22); a third wiring layer (63) spaced apart from the first wiring layer (61) and the second wiring layer (62), and electrically connected to the second terminal (52); and a fourth wiring layer (64) electrically connected to the third wiring layer (63), the signal wiring (66, 67) comprising: a first gate wiring layer (66) on a level different from a level of the main wiring (61, 62, 63, 64) in the first direction and electrically connected to the first gate terminal (54); and a second gate wiring layer (67) on a level different from the level of the main wiring (61, 62, 63, 64) in the first direction and electrically connected to the second gate terminal (55), each of the first semiconductor elements (30) comprising: a first electrode (32) electrically connected to the first metal layer (21) and disposed on a first surface (S1) of the first semiconductor element (30); a second electrode (33) electrically connected to the second wiring layer (62) and disposed on a second surface (S2) of the first semiconductor element (30) that is opposite to the first surface (S1) of the first semiconductor element (30); and a first gate electrode (34) electrically connected to the first gate wiring layer (66) and disposed on the second surface (S2) of the first semiconductor element (30), and each of the second semiconductor elements (31) comprising: a third electrode (35) electrically connected to the second metal layer (22) and disposed on a first surface (S1) of the second semiconductor element (31); a fourth electrode (36) electrically connected to the fourth wiring layer (64) and disposed on a second surface (S2) of the second semiconductor element (31) that is opposite to the first surface (S1) of the second semiconductor element (31); and a second gate electrode (37) electrically connected to the second gate wiring layer (67) and disposed on the second surface (S2) of the second semiconductor element (31), wherein the signal wiring (66, 67, 68, 69) further comprises: a first source sense wiring layer (68) electrically connected to each of the second electrodes (33) and the first source sense terminal (56); and a second source sense wiring layer (69) electrically connected to each of the fourth electrodes (36) and the second source sense terminal (57).
  2. The semiconductor device (100) according to claim 1, further comprising: a first conductor layer (41) between the second electrode (33) and the second wiring layer (62); a first gate conductor layer (46) between the first gate electrode (34) and the first gate wiring layer (66); a second conductor layer (42) between the fourth electrode (36) and the fourth wiring layer (64); a second gate conductor layer (47) between the second gate electrode (37) and the second gate wiring layer; a third conductor layer (43) between the second metal layer (22) and the second wiring layer (62); a fourth conductor layer (44) electrically connected to the first wiring layer (61) through a first connector (71); and a fifth wiring layer (65) disposed on the second substrate (12) and between the first connector (71) and the fourth conductor layer (44).
  3. The semiconductor device (100) according to claim 2, further comprising: a third metal layer (23) disposed on the first substrate (11) and adjacent to the second metal layer (22) in a second direction intersecting the first direction; and a fifth conductor layer (45) between the third metal layer (23) and the fourth wiring layer (64).
  4. The semiconductor device (100) according to claim 3, further comprising: a sixth conductor layer (81) between the first electrode (32) and the first metal layer (21); and a seventh conductor layer (82) between the third electrode (35) and the second metal layer (22).
  5. The semiconductor device (100) according to claim 3, wherein a bonded interface between the second wiring layer (62) and the first conductor layer (41), a bonded interface between the second wiring layer (62) and the third conductor layer (43), a bonded interface between the fourth wiring layer (64) and the second conductor layer (42), a bonded interface between the fourth wiring layer (64) and the fifth conductor layer (45), and a bonded interface between the fifth wiring layer (65) and the fourth conductor layer (44) are located on an identical plane that is orthogonal to the first direction.
  6. The semiconductor device (100) according to claim 1, wherein a passive element is connected to the signal wiring (66, 67).
  7. The semiconductor device (100) according to claim 1, wherein a current flows in the first wiring layer (61) and in the second wiring layer (62) in directions opposite to each other in the second direction, and a current flows in the third wiring layer (63) and in the fourth wiring layer (64) in directions opposite to each other in the second direction.
  8. The semiconductor device (100) according to claim 1, wherein part of the first wiring layer (61) is directly above part of the second wiring layer (62) in the first direction, and part of the third wiring layer (63) is directly above part of the fourth wiring layer (64) in the first direction.
  9. The semiconductor device (100) according to claim 1, further comprising a shield layer (84) between the main wiring (61, 62, 63, 64) and the signal wiring (66, 67).
  10. The semiconductor device (100) according to claim 9, wherein the shield layer (84) is disposed in the second substrate (12).
  11. The semiconductor device (100) according to claim 1, wherein each of the first and second semiconductor elements (30,31) is encapsulated with resin (83) on sides connecting the first and second surfaces (S1, S2) thereof.

Description

FIELD Embodiments described herein relate generally to a semiconductor device. BACKGROUND In a power module of the related art, semiconductor elements are mounted on a substrate. Electrodes of the semiconductor elements are electrically connected to a circuit on the substrate with wiring made of thin metal wire, for example. The wiring has an inductance (Ls), and when a current flows in the wiring, an electromotive force is induced. A surge voltage generated when the semiconductor device is turned off is represented by a product of a current change rate and the inductance. In accordance with an increase in switching speed, the current change rate increases, and accordingly, the surge voltage increases. When the surge voltage exceeds a predetermined voltage, the semiconductor elements may be damaged. For this reason, there is a need for decreasing the induced electromotive force. As an example of decreasing the induced electromotive force, there is a method of opposing wirings where the current flows in reverse directions. However, when using a two-dimensional circuit formed on an insulated circuit board, countercurrents of the wirings produce an insufficient effect of canceling the induced electromotive force. Moreover, when the wirings are disposed on the single insulated circuit board, the semiconductor elements cannot be integrated at high density. EP 3 349 249 A2 discloses a parallel plate waveguide for power circuits. US 2013/0258628 A1 discloses a power converter. US 2018/0233421 A1 discloses semiconductor package, assembly and module arrangements for measuring gate-to-emitter/source voltage. DESCRIPTION OF THE DRAWINGS Figs. 1A and 1B are each a plan view of a semiconductor device according to a first embodiment.Fig. 2A is a cross-sectional view taken along line A-A' in Fig. 1B.Fig. 2B is a cross-sectional view taken along line B-B' in Fig. 1B.Fig. 2C is a cross-sectional view taken along line C-C' in Fig. 1BFig. 3A is a cross-sectional view taken along line D-D' in Fig. 1B.Fig. 3B is a cross-sectional view taken along line E-E' in Fig. 1B.Fig. 3C is a cross-sectional view taken along line F-F' in Fig. 1B.Fig. 3D is a cross-sectional view taken along line G-G' in Fig. 1B.Fig. 4 illustrates an equivalent circuit of the semiconductor device according to the first embodiment.Fig. 5 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment.Fig. 6 is a cross-sectional view of a semiconductor device according to another modification of the first embodiment.Fig. 7 is a cross-sectional view of a semiconductor device according to a comparative example.Fig. 8 is a cross-sectional view of a semiconductor device according to a second embodiment.Fig. 9 is a perspective view of a front surface side and a rear surface side of a first semiconductor element or a second semiconductor element, included in the semiconductor device according to embodiments. DETAILED DESCRIPTION According to the invention a semiconductor device is disclosed as recited in claim 1. Further embodiments are disclosed in the dependent claims. Embodiments provide a semiconductor device that can increase integration of semiconductor elements and can decrease an induced electromotive force during operation. In general, according to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first metal layer, a second metal layer, a first semiconductor element, a second semiconductor element, a first terminal, a second terminal, a third terminal, a first gate terminal, and a second gate terminal. The first metal layer is disposed on the first substrate. The second metal layer is disposed on the first substrate and spaced apart from the first metal layer. The second substrate is spaced apart from the first substrate in a first direction and includes a main wiring and a signal wiring. The main wiring includes a first wiring layer electrically connected to the first metal layer, a second wiring layer electrically connected to the second metal layer, a third wiring layer spaced apart from the first wiring layer and the second wiring layer, and a fourth wiring layer electrically connected to the third wiring layer. The signal wiring includes a first gate wiring layer on a level different from a level of the main wiring in the first direction, and a second gate wiring layer on a level different from the level of the main wiring in the first direction. The first semiconductor element is disposed on the first metal layer and includes a first electrode, a second electrode, and a first gate electrode. The first electrode is electrically connected to the first metal layer and disposed on a first surface of the first semiconductor element. The second electrode is electrically connected to the second wiring layer and disposed on a second surface of the first semiconductor element that is opposite to the first surface of the first semiconductor element. The first gate electrode is elect