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EP-4086940-B1 - METHOD OF MAKING SUPERCONDUCTING THROUGH SUBSTRATE VIAS

EP4086940B1EP 4086940 B1EP4086940 B1EP 4086940B1EP-4086940-B1

Inventors

  • Jenei, Máté
  • Landra, Alessandro
  • PALMA, MARIO
  • CHAN, KOK WAI
  • Ahmad, Hasnain
  • VENKATESH, Manjunath Ramachandrappa
  • LIU, WEI
  • YANG, LILY
  • LI, TIANYI
  • Orgiazzi, Jean-Luc
  • Ockeloen-Korppi, Caspar

Dates

Publication Date
20260513
Application Date
20220429

Claims (11)

  1. A method for forming superconducting through substrate vias in a substrate (101), the method comprising: etching (202) one or more openings in the substrate (101), the etched openings extending from a first side of the substrate (101) partially through the substrate (101) towards a second side of the substrate (101); depositing (203) a seed layer (103) over the first side of the substrate (103) and the interior surfaces of the one or more etched openings in the substrate (101); forming (204) a resist or hardmask (104) on the first side of the substrate (101) above the seed layer (103), such that the resist or hardmask (104) comprises one or more openings (111) aligned with the etched openings in the substrate (101), wherein the one or more openings (111) in the resist or hardmask (104) are aligned with the etched openings in the substrate (101) such that the edges of the resist or hardmask (104) are aligned with the edges of the seed layer (103) and only the areas of the seed layer (103) that lie within the openings in the substrate (101) are exposed; filling (205) the etched openings in the substrate (101) with a superconducting filler material (105) by electroplating; and thinning the substrate (101) by removing (207) material from the second side of the substrate (101) until the deposited seed layer (103) is exposed on the second side of the substrate (101).
  2. The method of claim 1, wherein the electroplating is DC or pulse electroplating.
  3. The method of any preceding claim, wherein filling (205) the etched opening with superconducting filler material (105) is performed by electrodeless electroplating in which and anode made of an inert conductive material is used.
  4. The method of any preceding claim, wherein filling (205) the etched opening with superconducting filler material (105) is performed using an anode formed of the superconducting filler material (105).
  5. The method of any preceding claim, wherein the superconducting filler material (105) is rhenium or indium.
  6. The method of any preceding claim, wherein before etching (202) the one or more openings in the substrate (101) the method comprises forming (201) a second resist or second hardmask (102), the second resist or second hardmask (102) comprising one or more openings (110) through which the substrate (101) is exposed, wherein the one or more openings in the substrate (101) are etched via the one or more openings (110) in the second resist or second hardmask (102).
  7. The method of any preceding claim, wherein removing (207) material from the second side of the substrate (101) is carried out by chemical mechanical polishing, dry blanket etching, physical grinding or chemical etching.
  8. The method of claim 7, wherein thinning the substrate comprises bonding (206) the first side of the substrate (101) to a second substrate (106), performing chemical mechanical polishing of the second side of the substrate (101) until the deposited seed layer (103) is exposed on the second side of the substrate (101) and debonding (208) the substrate (101) from the second substrate (106) to expose the seed layer (103) and filler material (105) on the first side of the substrate (101).
  9. The method of any preceding claim, wherein following thinning the substrate, the method comprises depositing a base metal layer (107) on the first or second side of the substrate (101).
  10. The method of claim 9, wherein following depositing the base metal layer (107), the method comprises patterning the base metal layer (107), wherein patterning the base metal layer (107) comprises depositing a resist on the base metal layer (107) by spin coating.
  11. The method of claim 9 or 10, wherein patterning the base metal layer (107) comprises forming components of a quantum processing unit.

Description

Technical Field The invention relates to the fabrication of high component density integrated circuit devices. Background In 3D integrated circuit devices, the integrated circuit components occupy not just a single substrate side, but are distributed on both sides of a substrate and/or on the sides of multiple unified dice, e.g. in a stack. The distribution of circuit components on different layers or design faces provides more flexibility on qubit chip design and also higher component density. The superconducting through silicon/substrate via (STSV) technology is a core aspect of high-qubit density quantum processing units, in which the two sides of a substrate are electrically connected by a (partially) metallized opening. Mitigating losses in STSVs is necessary to create a versatile 3D-integrated qubit design, in which the STSV can be the part of a qubit, readout structure, or control lines. Furthermore, in existing hollow STSV structures, securing a wafer during resist spinning - an essential step in the formation of quantum processing unit components on the wafer - requires additional fabrication steps because the hollow STSV structures prevent the formation of a sufficiently strong vacuum to hold the wafer on the spinning chuck. These additional fabrication steps may also introduce impurities that can negatively affect the performance of the superconducting connection. Methods of fabricating TSVs exist in prior art. For example, publications US 2013/140688 A1, US 2008/299759 A1, WO 2019/117975 A1, and US 2018/005887 A1 each present a different method. However, each of these methods comprises fabrication steps, such as chemical mechanical polishing of a metallic layer subsequently used to fabricate electrical components, which may compromise the electrical characteristics of the manufactured product. Summary According to a first aspect of the invention, a method for forming superconducting through substrate vias in a substrate is provided. The method comprises: etching one or more openings in the substrate, the etched openings extending from a first side of the substrate partially through the substrate towards a second side of the substrate;depositing a seed layer over the first side of the substrate and the interior surfaces of the one or more etched openings in the substrate;forming a resist or hardmask on the first side of the substrate above the seed layer, such that the resist or hardmask comprises one or more openings aligned with the etched openings in the substrate, wherein the one or more openings in the resist or hardmask are aligned with the etched openings in the substrate such that the edges of the resist or hardmask are aligned with the edges of the seed layer and only the areas of the seed layer that lie within the openings in the substrate are exposed;filling the etched openings in the substrate with a superconducting filler material by electroplating; andthinning the substrate by removing material from the second side of the substrate until the deposited seed layer is exposed on the second side of the substrate. The electroplating may be DC or pulse electroplating. Filling the etched opening with superconducting filler material is performed by electrodeless electroplating. Lanthanum superconducting filler material may be deposited by this process. Filling the etched opening with superconducting filler material may be performed using an anode formed of the superconducting filler material. The superconducting filler material may be rhenium or indium. Before etching the one or more openings in the substrate the method may comprise forming a second resist or second hardmask, the second resist or second hardmask comprising one or more openings through which the substrate is exposed, wherein the one or more openings in the substrate are etched via the one or more openings in the second resist or second hardmask. Removing material from the second side of the substrate may be carried out by chemical mechanical polishing, dry blanket etching, physical grinding or chemical etching. Thinning the substrate may comprise bonding the first side of the substrate to a second substrate, performing chemical mechanical polishing of the second side of the substrate until the deposited seed layer is exposed on the second side of the substrate and debonding the substrate from the second substrate to expose the seed layer and filler material on the first side of the substrate. Following thinning the substrate, the method may comprise depositing a base metal layer on the first or second side of the substrate. Following depositing the base metal layer, the method may comprise patterning the base metal layer, wherein patterning the base metal layer comprises depositing a resist on the base metal layer by spin coating. Patterning the base metal layer may comprise forming components of a quantum processing unit. Brief Description of the Drawings Figures 1A to 1I show the intermediate results of each step of the fa