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EP-4089539-B1 - STORAGE DEVICE AND OPERATING METHOD OF STORAGE CONTROLLER

EP4089539B1EP 4089539 B1EP4089539 B1EP 4089539B1EP-4089539-B1

Inventors

  • JEONG, SUNGWON
  • KWON, MOONSANG
  • HEO, Younghoi
  • LEE, JAESHIN
  • JUNG, EUN

Dates

Publication Date
20260506
Application Date
20220117

Claims (10)

  1. A storage device (10, 10a) comprising: a non-volatile memory (200, 200a); and a storage controller (100, 100a) configured to control the non-volatile memory (200, 200a), wherein the storage controller (100, 100a) comprises: a command and address generator (110, 110a) configured to generate a first command, an address, and a second command as command set, the second command including an error detection signal for detecting a communication error in the first command and the address; an error detection module (120) configured to generate the error detection signal from the first command and the address; and an interface circuit (130, 170) configured to sequentially transmit the first command, the address, and the second command as the command set to the non-volatile memory (200, 200a), wherein the first command indicates a type of a memory operation to be performed in the non-volatile memory (200, 200a), and the second command corresponds to a confirm command.
  2. The storage device (10, 10a) of claim 1, wherein the error detection signal comprises a 1-bit signal.
  3. The storage device (10, 10a) of claim 1, wherein the error detection module (120) is further configured to generate a parity bit from the first command and the address, wherein the parity bit is generated as the error detection signal.
  4. The storage device (10, 10a) of claim 1, wherein the error detection module (120) is further configured to generate a cyclic redundancy check, CRC, value from the first command and the address, wherein the CRC value is generated as the error detection signal.
  5. The storage device (10, 10a) of claim 1, wherein the error detection module (120) is further configured to generate a checksum from the first command and the address, wherein the checksum is generated as the error detection signal.
  6. The storage device (10, 10a) of claim 1, wherein the interface circuit (130, 170) is further configured to: transmit, to the non-volatile memory (200, 200a), a command latch enable signal having an enable level in a transmission period of the first command and the second command; and transmit, to the non-volatile memory (200, 200a), an address latch enable signal having an enable level in a transmission period of the address.
  7. The storage device (10, 10a) of claim 1, wherein the non-volatile memory (200, 200a) is configured to: detect the communication error in the first command and the address, based on the error detection signal; and transmit an error message to the storage controller (100, 100a) when the communication error is detected.
  8. The storage device (10, 10a) of claim 7, wherein the interface circuit (130, 170) sequentially transmits the first command, the address, and the second command again to the non-volatile memory (200, 200a) based on the error message.
  9. The storage device (10, 10a) of claim 1, wherein the storage controller (100, 100a) further comprises a machine learning module (190) configured to predict the communication error in the first command and the address.
  10. The storage device (10, 10a) of claim 9, wherein the machine learning module (190) is further configured to control the command and address generator (110, 110a) and the error detection module (120) to transmit the error detection signal to the non-volatile memory (200, 200a) when the communication error is predicted and to not transmit the error detection signal to the non-volatile memory (200, 200a) when the communication error is not predicted.

Description

BACKGROUND The present disclosure relates to a memory device, and more particularly, to a storage controller having a communication error detection function of a command/address, a storage device including the storage controller, and an operating method of the storage controller. The storage controller may use an error correction code (ECC) engine to detect and correct errors occurring during transmission or reception of data. However, a storage controller of the related art does not have a configuration for detecting errors occurring during transmission of a command and an address. Therefore, even when an error occurs in a command and an address transmitted to a non-volatile memory from the storage controller, the error is difficult to detect and correct. US 2019/065237 A1 discloses: Methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. US 2014/089755 A1 discloses: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion. SUMMARY The invention is defined by the appended independent claim 1. It is an aspect to provide a storage device capable of detecting a communication error in a command and an address. According to an aspect of an embodiment, there is provided a storage device comprising a non-volatile memory; and a storage controller configured to control the non-volatile memory. The storage controller comprises a command and address generator configured to generate a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address; an error detection module configured to generate the error detection signal from the first command and the address; and an interface circuit configured to sequentially transmit the first command, the address, and the second command as command set to the non-volatile memory, wherein the first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a block diagram of a storage device according to an embodiment;FIGS. 2A and 2B are timing diagrams illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment;FIG. 3 illustrates a method of performing a read operation between a storage controller and a non-volatile memory according to an embodiment;FIGS. 4A and 4B are timing diagrams illustrating communication between a storage controller and a non-volatile memory during a write operation of the non-volatile memory according to an embodiment;FIG. 5 illustrates a method of performing a write operation between a storage controller and a non-volatile memory according to an embodiment;FIG. 6 is a detailed block diagram of a storage controller according to an embodiment;FIG. 7 is a detailed block diagram of a non-volatile memory according to an embodiment;FIG. 8 is a block diagram of a storage device according to an embodiment;FIGS. 9A to 9C are timing diagrams illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment;FIGS. 10A to 10C are timing diagrams illustrating communication between a storage controller and a non-