EP-4095668-B1 - NETWORK STORAGE DEVICE STORING LARGE AMOUNT OF DATA
Inventors
- LEE, CHANGDUCK
- SHIN, SEUNGYEOP
- YANG, KYUNGBO
- OH, HWASEOK
Dates
- Publication Date
- 20260506
- Application Date
- 20190412
Claims (11)
- A network storage device (200) comprising: a buffer memory (220) configured to exchange data with a network fabric over an Ethernet switch (100); a NVM cluster (280) comprising a plurality of nonvolatile memory devices (240, 250, 260, 270) and a plurality of NVM switches (230, 232, 234), the plurality of NVM switches configured to expand a capacity of the NVM cluster by expansion-connecting at least one or more of the plurality of nonvolatile memory devices and at least one or more of the plurality of NVM switches to a flash interface (219); and a network storage controller (210), different from the plurality of NVM switches, configured to connect to the Ethernet switch through a first port (PT1), the buffer memory though a second port (PT2), and the NVM cluster through a third port (PT3), wherein the network storage controller includes a host interface (215) to communicate with the Ethernet switch through the first port, the flash interface to exchange data with the NVM cluster through the third port, and a buffer manager (217) to control read and write operations of the buffer memory through the second port, wherein the network storage controller directly connects to the at least one or more of the plurality of nonvolatile memory devices of the NVM cluster through a first channel (CH1) without an intervening NVM switch, and the network storage controller connects to the at least one or more of the plurality of NVM switches through a second channel (CH2) which is independent of the first channel, wherein the network storage controller (210) is configured to directly translate a first command or data provided from the Ethernet switch (100) and having a network transmission format for supporting an Ethernet protocol, an NVMe-oF protocol, and an NVMe protocol into a second command or data format for controlling the plurality of nonvolatile memory devices (240, 250, 260, 270) at a single protocol layer, wherein the network storage controller 210 is configured to load/store the first command and data transmitted from the network fabric to the nonvolatile memory devices (240, 250, 260, 270) after being processed through a command path and a data path, which are separate from each other.
- The network storage device (200) of claim 1, the network storage controller (210) further connects to at least one or more cascade NVM switches (232, 234) through a third channel (CH3) to add more nonvolatile memory devices (240, 250, 260, 270) into the NVM cluster (280), wherein the first channel (CH1), the second channel (CH2) and the third channel (CH3) are provided by the third port (PT3).
- The network storage device (200) of claim 1 or claim 2, further comprising at least one or more cascaded NVM switches (230, 232, 234) connected with the flash interface (219) of the network storage controller (210) through the second channel (CH2).
- The network storage device (200) of any preceding claim, wherein the network storage controller (210) further comprises a fourth port (PT4) to communicate with an external processor (211b).
- The network storage device (200) of any preceding claim, wherein a switch (232) of the plurality of NVM switches (230, 232, 234) comprises a first switch controller (231) configured to update address mapping when a nonvolatile memory device (250) is added to or removed from the NVM cluster (280).
- The network storage device (200) of any preceding claim, wherein at least one of the plurality of nonvolatile memory devices (240, 250, 260, 270) includes a plurality of raw NAND flash memory devices (Raw_NANAD_1i) connected to a NVM switch among the plurality of NVM switches (230, 232, 234).
- The network storage device (200) of claim 1, wherein a further switch (234) of the plurality of NVM switches (230, 232, 234) comprises a second switch controller (235) configured to access one of the at least one or more of the plurality of nonvolatile memory devices (240, 250, 260, 270) responsive to the second command and to map a first address provided from the network storage controller (210) onto a second address of the plurality of nonvolatile memory devices.
- The network storage device (200) of claim 1 or claim 7, wherein the plurality of NVM switches (230, 232, 234) comprises: a first NVM switch configured to perform interfacing with the network storage controller (210); and a second NVM switch configured to perform interfacing with the first NVM switch.
- The network storage device (200) of claim 8, wherein the first NVM switch is configured to map the second address provided from the network storage controller (210) onto a third address of a first nonvolatile memory connected to the first NVM switch and the second NVM switch.
- The network storage device of claim 9, wherein the second NVM switch is configured to map the third address provided from the first NVM switch onto a fourth address of a second nonvolatile memory connected to the second NVM switch.
- The network storage device (200) of any preceding claim, wherein the network storage controller (210) is implemented with a single chip.
Description
TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly to network storage devices storing a large amount of data. BACKGROUND Solid state drive (hereinafter referred to as SSD) is an example of a flash memory based mass storage device. The use of SSDs has recently diversified as the demand for mass storage has increased. For example, SSDs may be characterized as subdivided into SSDs implemented for use as servers, SSDs implemented for client use, and SSDs implemented for data centers, among various other implementations. An SSD interface is used to provide the highest speed and reliability suitable for the implementation. For the purpose of satisfying the requirement of high speed and reliability, the nonvolatile memory express (NVMe) interface specification which is based on Serial Advanced Technology Attachment (SATA), Serial Attached Small Component Interface (SAS), or Peripheral Component Interconnect Express (PCIe) has been actively developed and applied. Currently, SSD interfaces that enable ease of expandability in systems such as large-capacity memory centers are actively being developed. In particular, an NVMe over fabrics (NVMe-oF) specification is actively being developed as a standard for mounting an SSD on a network fabric such as an Ethernet switch. The NVMe-oF supports an NVMe storage protocol through extensive storage networking fabrics (e.g., an Ethernet, a Fibre Channel™, and InfiniBand™). The NVMe storage protocol is also applied to an NVMe SSD. Accordingly, an interface of storage including an NVMe SSD translates a protocol for a network fabric into the NVMe-oF protocol or has a function of a data buffer. However, in this case, since there is a need for protocol translation corresponding to a plurality of protocol layers, an increase in latency is inevitable. Accordingly, to reduce latency and make capacity expansion easy, instead of using an NVMe SSD, there is a need for a technology for using a nonvolatile memory device or a nonvolatile memory array as a storage medium and performing multi-protocol translation efficiently. US 2017/052916 A1 describes a host connected to a switch using a PCI Express (PCIe) link. At the switch, the packets are received and routed as appropriate and provided to a conventional switch network port for egress. The conventional networking hardware on the host is substantially moved to the port at the switch, with various software portions retained as a driver on the host. This saves cost and space and reduces latency significantly. As networking protocols have multiple threads or flows, these flows can correlate to PCIe queues, easing QoS handling. The data provided over the PCIe link is essentially just the payload of the packet, so sending the packet from the switch as a different protocol just requires doing the protocol specific wrapping. In some embodiments, this use of different protocols can be done dynamically, allowing the bandwidth of the PCIe link to be shared between various protocols. US 9,565,269 B2 describes a processing device configured to receive a message encapsulating an input/output (I/O) command from a remote computing device. The processing device identifies one or more physical storage devices to be accessed to satisfy the I/O command. The processing device then sends, to each physical storage device of the one or more physical storage devices, one or more non-volatile memory express (NVMe) commands directed to that physical storage device. SUMMARY The present invention provides a network storage device connected with a network fabric according to the appended claims. Embodiments of the inventive concepts provide an Ethernet storage device for simplifying a controller structure of a network storage device and providing ease of expansion. Embodiments of the disclosed concepts provide a network storage device connected with a network fabric. The network storage device includes a network storage controller that performs interfacing with the network fabric, and translates and processes a command provided through the network fabric; and a nonvolatile memory cluster that exchanges data with the network storage controller under control of the network storage controller. The nonvolatile memory cluster includes a first nonvolatile memory array connected with the network storage controller through a first channel, a nonvolatile memory switch connected with the network storage controller through a second channel, and a second nonvolatile memory array communicating with the network storage controller under control of the nonvolatile memory switch. Embodiments of the disclosed concepts further provide a network storage device that includes a network storage controller that translates a first command provided through a network switch into a second command for controlling a nonvolatile memory and outputs the second command by using an interface; and a nonvolatile memory cluster including the nonvolatile me