EP-4104013-B1 - ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE

EP4104013B1EP 4104013 B1EP4104013 B1EP 4104013B1EP-4104013-B1

Inventors

WANG, KE
DI, Muxin
Liang, Zhiwei
WANG, GUOQIANG
GU, RENQUAN
SONG, XIAOXIN
ZHU, XIAOYAN
LIU, Yingwei
CAO, ZHANFENG

Dates

Publication Date: 20260506
Application Date: 20200324

Claims (15)

An array substrate, comprising a display area (DA) having a plurality of subpixels (SP); wherein the display area (DA) comprises a regular display sub-area (RDA) and a display-bonding sub-area (DBA); the plurality of subpixels (SP) comprises a plurality of first subpixels (SP1) in the display-bonding sub-area (DBA) and a plurality of second subpixels (SP2) in the regular display sub-area (RDA); wherein the array substrate comprises: a base substrate (BS) extending throughout the regular display sub-area (RDA) and the display-bonding sub-area (DBA); and a plurality of thin film transistors (TFT) on a first side (S1) of the base substrate (BS) and respectively in the plurality of subpixels (SP); characterized in that , a respective one of the plurality of first subpixels (SP1) comprises: a bonding pad (BP) on a second side (S2) of the base substrate (BS), wherein the second side (S2) is opposite to the first side (S1); a lead line (LL) electrically connecting a respective one of the plurality of thin film transistors (TFT) to the bonding pad (BP), wherein the lead line (LL) is unexposed in the array substrate; and a via (V) extending through the base substrate (BS); wherein the lead line (LL) extends from the first side (S1) to the second side (S2) of the base substrate (BS) through the via (V), to connect to the bonding pad (BP).
The array substrate of claim 1, further comprising an insulating layer (IN) on the second side (S2) of the base substrate (BS) and limited in the display-bonding sub-area (DBA); wherein the bonding pad (BP) is on a side of the insulating layer (IN) away from the base substrate (BS); and the via (V) extends through the base substrate (BS) and the insulating layer (IN).
The array substrate of claim 2, wherein the base substrate (BS) has a first thickness t1 in a region corresponding to the bonding pad (BP), and has a second thickness t2 in a region outside the region corresponding to the bonding pad (BP); the insulating layer (IN) has a third thickness t3; and t 2 > t 1 + t 3 .
The array substrate of claim 1, further comprising a recess (RES) in a region corresponding to the bonding pad (BP) for bonding the bonding pad (BP) with an integrated circuit (IC); wherein the recess (RES) is on the second side (S2) of the base substrate (BS), exposing a surface of the bonding pad (BP), Preferably, the array substrate further comprises an insulating layer (IN) on the second side (S2) of the base substrate (BS) and limited in the display-bonding sub-area (DBA); wherein the bonding pad (BP) is on a side of the insulating layer (IN) away from the base substrate (BS); the via (V) extends through the base substrate (BS) and the insulating layer (IN); and the recess (RES) exposes the surface of the bonding pad (BP) and a surface of the insulating layer (IN), Preferably, the base substrate (BS) has a first thickness t1 in a region corresponding to the bonding pad (BP), and has a second thickness t2 in a region outside the region corresponding to the bonding pad (BP); the insulating layer (IN) has a third thickness t3; the recess (RES) has a fourth thickness t4; and t2 is substantially equal to a sum of t1, t3, and t4.
The array substrate of claim 2, further comprising a plurality of additional insulating layers (AIN), each of which partially extending into the via (V), Preferably, wherein the plurality of additional insulating layers (AIN) comprise a passivation layer (PVX) extending throughout the display area (DA); wherein the passivation layer (PVX) is on the first side (S1) of the base substrate (BS), and at least partially covering a lateral side of the via (V); and the lead line (LL) is on a side of the passivation layer (PVX) away from the insulating layer (IN), Preferably, wherein the plurality of additional insulating layers (AIN) comprise further comprises a barrier layer (BL) extending throughout the display area (DA); wherein the barrier layer (BL) is on a side of the passivation layer (PVX) and the lead line (LL) away from the base substrate (BS); and the insulating layer (IN), the bonding pad (BP), the passivation layer (PVX), and the barrier layer (BL) encapsulate the lead line (LL) inside the array substrate, Preferably, wherein the plurality of additional insulating layers (AIN) comprise further comprises a buffer layer (BUF) extending throughout the display area (DA); wherein the respective one of the plurality of thin film transistors (TFT) comprises an active layer (ACT) on a side of the buffer layer (BUF) away from the base substrate (BS).
The array substrate of any one of claims 1 to 5, wherein the base substrate (BS) is a flexible base substrate.
A display apparatus, comprising the array substrate of any one of claims 1 to 6, and one or more integrated circuits (IC) connected to the array substrate.
A method of fabricating an array substrate, comprising forming a display area (DA) having a plurality of subpixels (SP); wherein forming the display area (DA) comprises forming a regular display sub-area (RDA) and forming a display-bonding sub-area (DBA); forming the plurality of subpixels (SP) comprises forming a plurality of first subpixels (SP1) in the display-bonding sub-area (DBA) and forming a plurality of second subpixels (SP2) in the regular display sub-area (RDA); wherein the method comprises forming a base substrate (BS) extending throughout the regular display sub-area (RDA) and the display-bonding sub-area (DBA); and forming a plurality of thin film transistors (TFT) on a first side (S1) of the base substrate (BS) and respectively in the plurality of subpixels (SP); characterized in that , forming a respective one of the plurality of first subpixels (SP1) comprises: forming a bonding pad (BP) on a second side (S2) of the base substrate (BS), wherein the second side (S2) is opposite to the first side (S1); forming a lead line (LL) electrically connecting a respective one of the plurality of thin film transistors (TFT) to the bonding pad (BP), wherein the lead line (LL) is unexposed in the array substrate; and forming a via (V) extending through the base substrate (BS); wherein the lead line (LL) is formed to extend from the first side (S1) to the second side (S2) of the base substrate (BS) through the via (V), to connect to the bonding pad (BP).
The method of claim 8, further comprising: providing a support substrate (SS); forming a debonding layer (DBL) limited in the display-bonding sub-area (DBA), and in a region corresponding to the bonding pad (BP); forming the bonding pad (BP) on a side of the debonding layer (DBL) away from the support substrate (SS); forming an insulating material layer (INM) limited in the display-bonding sub-area (DBA); forming a base substrate material layer (BSM) throughout the regular display sub-area (RDA) and the display-bonding sub-area (DBA), and on a side of the insulating material layer (INM) away from the support substrate (SS); and etching the insulating material layer (INM) and the base substrate material layer (BSM) to form the via (V) extending through the insulating material layer (INM) and the base substrate material layer (BSM) to expose a contacting surface (CS) of the bonding pad (BP), thereby forming an insulating layer (IN) limited in the display-bonding sub-area (DBA), and the base substrate (BS) on the insulating layer (IN).
The method of claim 9, further comprising forming a passivation material layer throughout the regular display sub-area (RDA) and the display-bonding sub-area (DBA), and on a side of the base substrate (BS) away from the support substrate (SS); and etching the passivation material layer to expose the contacting surface (CS) of the bonding pad (BP), thereby forming a passivation layer (PVX); wherein the passivation layer (PVX) is formed on the first side (S1) of the base substrate (BS), and at least partially covering a lateral side of the via (V).
The method of claim 10, further comprising forming the lead line (LL) of a side of the passivation layer (PVX) away from the base substrate (BS); wherein the lead line (LL) is formed to extend into the via (V) to connect to the bonding pad (BP).
The method of claim 11, further comprising forming a barrier layer (BL) throughout the regular display sub-area (RDA) and the display-bonding sub-area (DBA), and on a side of the lead line (LL) away from the base substrate (BS); forming a buffer layer (BUF) throughout the regular display sub-area (RDA) and the display-bonding sub-area (DBA), and on a side of the barrier layer (BL) away from the base substrate (BS); and forming an active layer (ACT) on a side of the buffer layer (BUF) away from the base substrate (BS).
The method of any one of claims 9 to 12, further comprising separating the debonding layer (DBL) from the bonding pad (BP) and the insulating layer (IN), thereby forming a recess (RES) in a region corresponding to the bonding pad (BP); wherein the recess (RES) is formed on the second side (S2) of the base substrate (BS), exposing a surface of the bonding pad (BP).
The method of claim 13, further comprising providing an integrated circuit (IC) in the recess (RES), the integrated circuit (IC) connecting to the surface of the bonding pad (BP) exposed in the recess (RES).
The method of any one of claims 8 to 14, further comprising forming a plurality of light emitting elements respectively in the plurality of subpixels (SP) including the plurality of first subpixels (SP1) and the plurality of second subpixels (SP2).

Description

TECHNICAL FIELD The present invention relates to display technology, more particularly, to an array substrate, a display apparatus, and a method of fabricating an array substrate. US patent application US20080049157A1 discloses a crystal liquid display and a method of manufacturing the same are disclosed. US patent application US2019067332A1 discloses an array substrate, a method for manufacturing the array substrate and a display device. Japanese patent application JP2015072361A discloses a display device including a flexible resin substrate SUB 1 (SUB 2) that has through holes H provided therein, a thin film transistor TFT that is provided on one surface of the resin substrate SUB 1 (SUB 2), and an electronic component FPC that is provided on the other surface of the resin substrate SUB 1 (SUB 2). BACKGROUND Technologies for fabricating a display apparatus having a narrow frame rapidly develops. Various methods used to fabricate a display apparatus having a narrow frame include, but are not limited to chip on film (COF), chip on plastic (COP), and gate driver on array (GOA). For example, chip on film (COF) and chip on plastic (COP) are used to fabricate a display panel having a narrow bottom portion of a frame. Gate driver on array (GOA) is used to fabricate a display having a narrow left side or a narrow right side of a frame. SUMMARY In one aspect, the present disclosure provides an array substrate, comprising a display area having a plurality of subpixels; wherein the display area comprises a regular display sub-area and a display-bonding sub-area; the plurality of subpixels comprises a plurality of first subpixels in the display-bonding sub-area and a plurality of second subpixels in the regular display sub-area; wherein the array substrate comprises a base substrate extending throughout the regular display sub-area and the display-bonding sub-area; and a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels; wherein a respective one of the plurality of first subpixels comprises a bonding pad on a second side of the base substrate, wherein the second side is opposite to the first side; a lead line electrically connecting a respective one of the plurality of thin film transistors to the bonding pad, wherein the lead line is unexposed in the array substrate; and a via extending through the base substrate; wherein the lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad. Optionally, the array substrate further comprises an insulating layer on the second side of the base substrate and limited in the display-bonding sub-area; wherein the bonding pad is on a side of the insulating layer away from the base substrate; and the via extends through the base substrate and the insulating layer. Optionally, the base substrate has a first thickness t1 in a region corresponding to the bonding pad, and has a second thickness t2 in a region outside the region corresponding to the bonding pad; the insulating layer has a third thickness t3; and t2 > (t1 + t3). Optionally, the array substrate further comprises a recess in a region corresponding to the bonding pad for bonding the bonding pad with an integrated circuit; wherein the recess is on the second side of the base substrate, exposing a surface of the bonding pad. Optionally, the array substrate further comprises an insulating layer on the second side of the base substrate and limited in the display-bonding sub-area; wherein the bonding pad is on a side of the insulating layer away from the base substrate; the via extends through the base substrate and the insulating layer; and the recess exposes the surface of the bonding pad and a surface of the insulating layer. Optionally, the base substrate has a first thickness t1 in a region corresponding to the bonding pad, and has a second thickness t2 in a region outside the region corresponding to the bonding pad; the insulating layer has a third thickness t3; the recess has a fourth thickness t4; and t2 is substantially equal to a sum of t1, t3, and t4. Optionally, the array substrate further comprises a plurality of additional insulating layers, each of which partially extending into the via. Optionally, the plurality of additional insulating layers comprise a passivation layer extending throughout the display area; wherein the passivation layer is on the first side of the base substrate, and at least partially covering a lateral side of the via; and the lead line is on a side of the passivation layer away from the insulating layer. Optionally, the plurality of additional insulating layers comprise further comprises a barrier layer extending throughout the display area; wherein the barrier layer is on a side of the passivation layer and the lead line away from the base substrate; and the insulating layer, the bonding pad, the passivation layer, and the barrier layer encapsulate the le