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EP-4104290-B1 - DIGITAL TRANSMITTER WITH HIGH POWER OUTPUT

EP4104290B1EP 4104290 B1EP4104290 B1EP 4104290B1EP-4104290-B1

Inventors

  • DE VREEDE, LEONARDUS CORNELIS NICOLAAS
  • ALAVI, Seyed Morteza
  • BOOTSMAN, Robert Jan
  • BEIKMIRZA, Mohammad Reza
  • MUL, Dieuwert Peter Nicolaas
  • HEERES, Rob
  • VAN RIJS, FREERK

Dates

Publication Date
20260506
Application Date
20210205

Claims (20)

  1. An RF transmitter (1), comprising: a gate-segmented power output stage (2) comprising a field-effect transistor having a plurality of gate fingers and/or gate runners (32) and a plurality of drain fingers and/or gate runners (31) that define a gate periphery, the field-effect transistor comprising a plurality of power output stage segments (3) that each correspond to a respective part of the gate periphery and that each have a respective power output stage segment input (4); and a digital driver (5) having control outputs (6) which are connected to corresponding ones of the respective power output stage segment inputs (4), the digital driver (5) being configured for switching one or more of the plurality of power output stage segments (3) between an on-mode and a cut-off mode in dependence of one or more input signals to obtain a modulated RF carrier signal at an output (7) of the gate-segmented power output stage (2).
  2. The RF transmitter (1) according to claim 1, wherein one or more adjacently arranged gate fingers and/or gate runners (32) are grouped into a respective gate segment (3a), wherein each power output stage segment (3) corresponds to one or more gate segments (3a).
  3. The RF transmitter (1) according to claim 1 or 2, wherein the one or more gate fingers and/or gate runners (32) are arranged in a pattern consisting of parallel rows, wherein at least one row comprises a plurality of gate fingers and/or gate runners (32), wherein the gate fingers and/or the gate runners (32) in the at least one row are aligned such that their width directions are in line.
  4. The RF transmitter (1) according to claim 3, wherein each row is associated with an active area that is continuous in the width direction such that a single active area is provided for each row, wherein the active area corresponds to all gate fingers and/or all the gate runners (32) in that row.
  5. The RF transmitter (1) according to any one of claims 1-4, wherein adjacent power output stage segments (3) share a drain finger and/or a drain runner (31).
  6. The RF transmitter (1) according to any one of claims 1-5, wherein all drain fingers and/or all the drain runners (31) extend from a drain bar (33).
  7. The RF transmitter (1) according to claim 6, wherein an operational frequency of the RF transmitter (1) ranges from 1 GHz to 50 GHz, and for which an absolute phase difference for signals propagating via adjacent power output stage segments (3) from the respective power output stage segment input (4) to the drain bar (33) is less than 5 degrees at the operational frequency for each pair of adjacent power output stage segments (3).
  8. The RF transmitter according to any one of claims 1-7, wherein the on-mode of a power output-stage segment (3) comprises a saturation state of the power output-stage segment (3).
  9. The RF transmitter according to any one of claims 1-8, wherein the digital driver (5) and gate-segmented power output stage (2) are implemented in different semiconductor technologies.
  10. The RF transmitter according to claim 9, wherein the digital driver (5) comprises a CMOS or SOI implemented digital driver.
  11. The RF transmitter according to claim 9 or 10, wherein the gate-segmented power output stage (2) comprises transistors of a laterally diffused metal-oxide-semiconductor (LDMOS) transistor type, and/or a GaN-based field-effect transistor type.
  12. The RF transmitter according to claim 11, wherein the transistors of the gate-segmented power output stage (2) are configured to have a threshold voltage for allowing the digital driver (5) to switch one or more of the plurality of power output stage segments (3) between the on-mode and cut-off mode in dependence of the control outputs (6).
  13. The RF transmitter according to any one of claims 1-12, further comprising a plurality of level shifters connected in between the control outputs (6) of the digital driver (5) and the power output stage segment inputs (4) of the gate-segmented power output stage (2).
  14. The RF transmitter according to any one of claims 1-13, wherein the digital driver (5) is provided in a first semiconductor die (8), and the gate-segmented power output stage (2) is provided in a second semiconductor die (9), the first semiconductor die (8) being different from the second semiconductor die (9), the digital driver (5) comprising a plurality of output terminals (8a) associated with the control outputs (6), the gate-segmented power output stage (2) comprising a plurality of input terminals (9a) associated with each power output stage segment input (4), further comprising connections (10) between respective output terminals (8a) on the first semiconductor die (8) and associated input terminals (9a) on the second semiconductor die (9).
  15. The RF transmitter according to claim 14, wherein the connections (10) comprise bond wires.
  16. The RF transmitter according to claim 14 wherein the connections (10) comprise interconnect film connections.
  17. The RF transmitter according to claim 14, wherein the connections (10) comprise flip-chip type connections.
  18. The RF transmitter according to any one of claims 1-17, wherein at least a part of the plurality of power output stage segments (3) has similar transistor dimensions, and the digital driver (5) comprises a thermometer bit style interface to the gate-segmented power output stage (2).
  19. The RF transmitter according to claim 18, wherein a further part of the plurality of power output stage segments (3) has unequal transistor dimensions, and the digital driver (5) comprises a binary bit word style interface to the gate-segmented power output stage (2).
  20. The RF transmitter according to any one of claims 1-19, wherein the RF transmitter (1) is a N-way Doherty transmitter having two or more gate-segmented power output stages (2A-2D).

Description

Field of the invention The present invention relates to an RF transmitter, comprising a power output stage and a digital driver connected to the power output stage, specifically suitable for high-speed and high-power applications, such as 5G mMIMO base stations. Background art The article by V. Diddi et al. entitled "Broadband digitally-controlled power amplifier based on CMOS/GaN combination," 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, 2016, pp. 258-261, discloses a digital RF power transmitter configuration with a control part and (single) amplifier stage, wherein the control part provides an analog signal to the power amplifier stage. International patent publication WO2018/132006 discloses a digitally-controlled power amplifier (DPA) including a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted power amplifier segments. Summary of the invention The present invention seeks to provide an improved RF transmitter implementation, which is specifically suited for high-speed, high-frequency, RF power applications, such as 5G massive Multiple Input Multiple Output (mMIMO) base stations. According to the present invention, an RF transmitter is provided in accordance with appended independent claim 1, comprising a gate-segmented power output stage, said power output stage comprising a field-effect transistor having a plurality of gate fingers and a plurality of drain fingers that define a gate periphery, the field-effect transistor comprising a plurality of power output stage segments that each correspond to a respective part of the gate periphery and that each have a respective power output stage segment input. The RF transmitter further comprises a digital driver having control outputs which are connected to corresponding ones of the respective power output stage segment inputs, the digital driver being configured for individually switching each of the power output stage segments between an on-mode and a cut-off mode, in dependence of one or more input signals, e.g. baseband signals in combination with one or more RF carrier signals and/or one or more RF reference clocks, to obtain a modulated RF carrier signal at an output of the gate-segmented power output stage. Typically, a power field-effect transistor comprises a plurality of gate fingers and a plurality of drain fingers to realize the required output power. According to the present invention, the gate-segmented power output stage corresponds to a gate-segmented version of this large transistor. To this end, the transistor is segmented into a plurality of smaller power output stage segments. Each of these segments corresponds to a respective part of the gate periphery. For example, the field-effect transistor may comprise n gate fingers, each having a gate width of / mm. In this respect, it is noted that the gate fingers and drain fingers are elongated structures. The longitudinal direction of the gate finger will be referred to as the width direction. Hence, in the abovementioned example, the gate periphery corresponds to n x l mm. It is possible to segment the field-effect transistor into p power output stage segments each corresponding to a part of the gate periphery, for example to n x l / p mm. Each power output stage segment may be formed by one or more of the plurality of gate fingers. For example, one or more adjacently arranged gate fingers can be grouped into a respective gate segment. Each power output stage segment may then correspond to one or more gate segments. The one or more gate fingers may be arranged in a pattern consisting of parallel rows, wherein at least one row comprises a plurality of gate fingers, wherein the gate fingers in said at least one row are aligned such that their width directions are in line. Such pattern closely resembles that of an unsegmented power transistor. Furthermore, each row can be associated with an active area that is continuous in the width direction such that a single active area is provided for each row, wherein the active area corresponds to all gate fingers in that row. The one or more gate fingers extend over a respective active area. More in particular, the one or more gate fingers are separated from the underlying semiconductor by a thin gate oxide. The thickness of the gate fingers is typically very small. To avoid high ohmic losses, thicker metal structures are used that also have the shape of fingers. These structures are connected to the gate fingers and are referred to as gate runners. Similar considerations hold for the drain fingers. These relatively thin fingers each form an ohmic contact to a respective drain region. Thicker finger shaped metal structures are then also used to minimize ohmic losses. As the shapes of the gate runners and gate fingers typically correspond, they will hereinafter both be referred to as gate fingers. Similar considerations hold for the drain fingers and the finger like metal struct