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EP-4116981-B1 - HIGH DENSITY MEMORY WITH REFERENCE CELL AND CORRESPONDING OPERATIONS

EP4116981B1EP 4116981 B1EP4116981 B1EP 4116981B1EP-4116981-B1

Inventors

  • YEH, TENG-HAO
  • LUE, HANG-TING
  • SUNG, CHENG-LIN
  • LIN, YUNG-FENG

Dates

Publication Date
20260506
Application Date
20210929

Claims (20)

  1. A memory, comprising: a data memory (900) comprising a plurality of memory cells on a plurality of bit lines (912, 913), a plurality of source select transistors (940), and a plurality of bit line transistors (930); a reference memory (950) comprising a plurality of memory cells (971, 960-963); a conversion circuitry (983, 1280) to convert signals from a group of memory cells (960-963) including more than one member in the plurality of memory cells (971, 960-963) in the reference memory (950) into a reference signal; and a sense amplifier (999, 1285), connected to the conversion circuitry (983) and to a bit line (932) in the plurality of bit lines (912, 913) in the data memory (900), to sense data stored in a selected memory cell (910) in the data memory (900) in response to comparison of a data signal from the selected memory cell (910) and the reference signal, wherein one of the plurality of the source select transistors (940) is decoded to select the selected memory cell (910) via a selected local source line (915), one of the plurality of the bit line transistors (930) is decoded by the selected memory cell (910) via the selected local bit line (913), and the sense amplifier (999, 1285) senses data stored in the selected memory cell (910) via the one of the plurality of the bit line transistors (930), the memory further comprising: a compensation capacitor (104), coupled to a signal path from the reference memory (950) to the sense amplifier (999, 1285).
  2. The memory of claim 1, wherein the group of memory cells (960-963) is disposed on a plurality of local reference bit lines (953, 1052, 1055, LRBLs), the plurality of local reference bit lines (953, 1052, 1055, LRBLs) being connected together for program operations in the reference memory (950).
  3. The memory of claim 1, wherein the reference memory (950) comprises a stack of horizontal word lines (951, 1001-1004) in respective levels of the stack and a set of vertical conductors (219B, 219S, 320, 321, 912), and the memory cells in the reference memory (950) have horizontal channels between adjacent horizontal word lines (951, 1001-1004) at the levels of horizontal word lines (951, 1001-1004) in the stack.
  4. The memory of claim 3, wherein the set of vertical conductors includes vertical conductors (219B, 219S, 320, 321, 912) extending to local reference source lines, and vertical conductors (219B, 219S, 320, 321, 912) extending to local reference bit lines (953, 1052, 1055, LRBLs), and the reference memory (950) includes reference bit line transistors (980) to connect local reference bit lines (953, 1052, 1055, LRBLs) of the group of memory cells to the conversion circuitry (983).
  5. The memory of claim 3, wherein the stack (1001) is disposed over a circuit level on a substrate, and reference bit line transistors (1261) are disposed in a reference bit line transistor region in the circuit level adjacent to the stack.
  6. The memory of claim 3, wherein the group of memory cells (960-963) is disposed on a plurality of local reference bit lines (953, 1052, 1055, LRBLs), the local reference bit lines (953, 1052, 1055, LRBLs)being disposed in a patterned conductor level over the stack, and including vertical connectors extending to a reference bit line transistor region.
  7. The memory of claim 1, wherein the conversion circuitry (1350) comprises a current mirror circuit (1351+1352) which produces a reference current in response to combined current from the group of memory cells (1312), and a current-to-voltage converter (1361).
  8. The memory of claim 1, wherein the memory cells in the group of memory cells (960-963) are disposed on a reference word line (1251), and including a reference word line driver (1250) to apply a word line reference voltage (V REF ) to the reference word line (1251), and to apply a deselect voltage to other word lines (1252) in the reference memory (950).
  9. The memory of claim 1, wherein the reference memory (950) comprises a stack structure (230, 801, 1001, 1051) including a plurality of slices (1220-1222, 1311-1313), each slice including a stack of horizontal word lines (951, 1001-1004) in respective levels of the stack and a set of vertical conductors (219B, 219S, 320, 321, 912), and the memory cells in the reference memory (950) have horizontal channels between adjacent horizontal word lines (951, 1001-1004)at the levels of horizontal word lines (951, 1001-1004) in the stack, and wherein the group of memory cells (960-963) is disposed in one of the slices of the plurality of slices (1220-1222, 1311-1313), and the stack of horizontal word lines (951, 1001-1004) includes a reference word line (1251) for the group of memory cells, and including a reference word line driver (1250) to apply a word line reference voltage (V REF ) to the reference word line (1251), and to apply a deselect voltage to other word lines (1252) in the reference memory (950).
  10. The memory of claim 1, wherein the reference memory (950) comprises a stack structure (230, 801, 1001, 1051) including a plurality of slices (1220-1222, 1311-1313), each slice including a stack of horizontal word lines (951, 1001-1004) in respective levels of the stack and a set of vertical conductors (219B, 219S, 320, 321, 912), and the memory cells in the reference memory (950) have horizontal channels between adjacent horizontal word lines (951, 1001-1004)at the levels of horizontal word lines (951, 1001-1004) in the stack, and wherein at least one of the plurality of slices (1220-1222, 1311-1313) includes the group of memory cells and at least one other one of the plurality of slices is disconnected from the conversion circuitry (983).
  11. The memory of claim 1,wherein: the reference memory including inactive memory cells (971) and the group of memory cells (960-963) from which the reference signal is converted is an active group of memory cells connected to local reference bit lines (953, 1052, 1055, LRBLs), and to a reference word line (951); and the conversion circuitry (983) converts signals on the local reference bit lines (953, 1052, 1055, LRBLs) from the active group of memory cells (960-963) into the reference signal (VR).
  12. The memory of claim 11, including a word line driver (1250) connected to the reference word line (1251) to apply a word line reference voltage (V REF ) and connected to other word lines (1252) in the reference memory (950) to apply a deselect voltage.
  13. The memory of claim 11, wherein the conversion circuitry (983) includes a summing node (1315) to sum current from the local reference bit lines (953, 1052, 1055, LRBLs) to form a combined current, and a current mirror circuit (1351+1352) to convert the combined current to a reference current (Iref) having reduced magnitude.
  14. The memory of claim 13, wherein the conversion circuitry (1280) includes a current-to-voltage converter (1361) to convert the reference current (Iref) to a reference voltage (VR), and to apply the reference voltage (VR) to the sense amplifier (999, 1285).
  15. The memory of claim 11, including a control circuit to program the inactive memory cells (971) to a first threshold state, and to program the active group of memory cells (960-963) to a second threshold state lower than the first threshold state.
  16. The memory of claim 15, wherein the control circuit applies an incremental step pulse program operation to the group of memory cells (960-963) to set the second threshold state.
  17. The memory of claim 11, including a control circuit to program the active group of memory cells (960-963) using an incremental step pulse program operation.
  18. The memory of claim 11, wherein the reference memory (950) comprises a stack structure (230, 801, 1001, 1051) including a plurality of slices (1220-1222, 1311-1313), each slice including a stack of horizontal word lines (951, 1001-1004) in respective levels of the stack and a set of vertical conductors (219B, 219S, 320, 321, 912), and the memory cells in the reference memory (950) have horizontal channels between adjacent horizontal word lines (951, 1001-1004)at the levels of horizontal word lines (951, 1001-1004) in the stack, and wherein the group of memory cells (960-963) is disposed in one of the slices of the plurality of slices (122-1222, 1311-1313), and the stack of horizontal word lines (951, 1001-1004) includes the reference word line (1251, 1252) for the group of memory cells (960-963), and including a reference word line driver (1250) to apply a word line reference voltage (V REF ) to the reference word line (1251), and to apply a deselect voltage to other word lines (1252) in the reference memory (950).
  19. The memory of claim 11, wherein the reference memory (950) comprises a stack structure (230, 801, 1001, 1051) including a plurality of slices (122-1222, 1311-1313), each slice including a stack of horizontal word lines (951, 1001-1004) in respective levels of the stack and a set of vertical conductors (219B, 219S, 320, 321, 912), and the memory cells in the reference memory (950) have horizontal channels between adjacent horizontal word lines (951, 1001-1004)at the levels of horizontal word lines (951, 1001-1004) in the stack, and wherein the group of memory cells is disposed in one of the slices of the plurality of slices (122-1222, 1311-1313), and the stack of horizontal word lines (951, 1001-1004) includes the reference word line for the group of memory cells, and wherein at least one of the plurality of slices (122-1222, 1311-1313) includes the group of memory cells and at least one other one of the plurality of slices (122-1222, 1311-1313) is disconnected from the conversion circuitry (983).
  20. The memory of claim 11, wherein the reference memory (950) comprises a stack structure (230, 801, 1001, 1051) including a plurality of slices (122-1222, 1311-1313), each slice (122-1222, 1311-1313) including a stack of horizontal word lines(951, 1001-1004) in respective levels of the stack, the stack in one of the plurality of slices (122-1222, 1311-1313) including a reference word line (1251), and a set of vertical conductors (219B, 219S, 320, 321, 912), and memory cells having horizontal channels between adjacent horizontal word lines (951, 1001-1004)at the levels of horizontal word lines (951, 1001-1004) in the stack; and the group of memory cells (960-963) being disposed in the first slice (1312), and memory cells in the other slices (1311, 1313) having vertical conductors (219B, 219S, 320, 321, 912) not connected to local reference bit lines (953, 1052, 1055, LRBLs).

Description

BACKGROUND Field The present invention relates to configurations of circuits for sensing data in memory integrated circuits, and more particularly in 3D non-volatile memory integrated circuits. Description of Related Art In high density memory, such as memory, process, voltage and temperature PVT, conditions have variant impact on performance of memory cells in different devices, and within individual devices. This issue is reflected in the design of sensing circuits. For example, some sense amplifier schemes involve generating a voltage from a selected memory cell, and comparing that voltage to a reference voltage. The voltages generated from selected memory cells can vary with PVT conditions across devices and across different parts of individual devices. These variations expand the sensing margins between data states required for the sensing circuits. When the sensing margins are high, high voltage sensing circuits are required for reliable operation. High voltage sensing circuits may be incompatible with, or difficult to implement with, modern memory technologies. Also, such variations in the reference voltage can contribute to expanded sensing margins. The reference voltage can be produced using a bandgap reference for example. However, bandgap reference circuits are not immune to process and temperature variations, and such variations may behave differently from the memory cells. This problem with PVT variations also contributes to expanding the sensing margins required for reliable operation. It is desirable to provide a technology that can improve sensing margins in high density memory, such as 3D flash memory. US 2007/002639A1 discloses a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. US 6 317 362 B1 discloses a pair of reference cells arranged in the same direction on a semiconductor substrate. The memory cell and the reference cell are coincident in their source/drain direction. The memory cell and the reference cell are coincident in their source/drain direction. A selection circuit selects the reference cell when the memory cell is selected, whereas the selection circuit selects the reference cell when the memory cell is selected. US 2016/005762 A1 discloses a vertical channel 3D NAND array for independent double gate operation, establishing two memory sites per frustum of a vertical channel column. The memory device has even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips. US 2019/319044 A1 discloses a memory structure including active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate. US 2006/233028 A1 discloses a Method and an apparatus for reference cell adjusting in a storage device. SUMMARY The scope of the invention is defined in the appended claims. Other aspects and advantages of the present technology can be seen on review of the drawings, the detailed description and the claims, which follow. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout view of an integrated circuit device including a data memory and a reference memory.FIG. 2 is a plan view of a 3D memory architecture which can be used to implement a tile such as that shown in FIG. 1.FIG. 3 is a cross-section in an X-Y plane of the pillars and a slice of the structure of FIG. 2.FIG. 4 is a cross-section on line A-A' of FIG. 3.FIG. 5 is a cross-section on line B-B' of FIG. 3.FIG. 6 is a circuit schematic diagram of portions of the memory structure of FIG. 2.FIG. 7 is a schematic circuit diagram showing a slice of the memory structure of FIG. 2.FIG. 8 is a perspective view illustrating a