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EP-4117022-B1 - A METHOD FOR SELECTIVE ETCHING OF NANOSTRUCTURES

EP4117022B1EP 4117022 B1EP4117022 B1EP 4117022B1EP-4117022-B1

Inventors

  • KHAN, MD Sabbir Ahmed
  • SUNDQVIST, JONAS
  • SUYATIN, Dmitry

Dates

Publication Date
20260506
Application Date
20170314

Claims (6)

  1. A method for forming a nanostructure, the method comprising: providing a substrate (51) having a first layer (53) and a photoresist layer (54), wherein the first layer (53) is arranged between the photoresist layer (54) and the substrate (51); lithography patterning the photoresist layer (54), thereby exposing areas (55) of the first layer (53); etching the exposed areas (55) of the first layer (53), thereby forming first recesses (56) in the first layer (55); removing the remaining photoresist layer (54), thereby forming ridges of the first layer between the first recesses (56) of the first layer (53); subjecting the ridges of the first layer (53) for a first dry etching process being an Atomic Layer Etching process comprising a first cyclic etch process where each cycle comprises subjecting the first layer for surface modification by one or more of chemisorption, deposition, conversion and extraction and subjecting the first layer for the particle beam consisting of particles having an energy of less than 1000 eV, wherein the particle beam having a direction being parallel with a surface normal to the first layer (53) within a deviation of ±20°, whereby selective etching of the ridges of the first layer (53) relative to walls (57) of the first recesses in the first layer (53) is achieved such that second recesses (59) in the first layer (53) are formed, the second recesses (59) in the first layer (53) having their openings at the ridges of the first layer (53); thereby a nanostructure consisting of a plurality of first fins (60) delimited by the first and second recesses (56, 59) in the first layer (53) are formed, the first fins (60) having a first pitch.
  2. The method according to claim 1, wherein the provided substrate (51) further comprises a hard mask layer (52) arranged directly beneath the first layer (53), wherein the acts of etching the exposed areas of the first layer (53) and subjecting the first layer (53) for the first dry etching process are performed such that the hard mask layer (52) is exposed.
  3. The method according to claim 2, wherein the provided substrate (51) further comprises a second layer, wherein the hard mask layer (52) is arranged in between the first and second layers, wherein the method further comprises: removing the hard mask layer (52) between the first fins (60), thereby exposing areas (65) of the second layer; etching the exposed areas (65) of the second layer, thereby forming first recesses (66) in the second layer; removing the first fins (60) and the remaining hard mask layer (52), thereby forming ridges of the second layer between the first recesses (66) in the second layer; subjecting the ridges of the second layer for a second dry etching process, wherein the second dry etching process being an Atomic Layer Etching process comprising a second cyclic etch process where each cycle comprises subjecting the second layer for surface modification by one or more of chemisorption, deposition, conversion and extraction and subjecting the second layer for the particle beam consisting of particles having an energy of less than 1000 eV, wherein the particle beam having a direction being parallel with a surface normal to the second layer within a deviation of ±20°; whereby selective etching of the ridges of the second layer relative to walls (67, 68) of the first recesses (66) in the second layer is achieved such that second recesses (69) in the second layer are formed, the second recesses (69) having their openings at the ridges of the second layer; thereby a nanostructure consisting of a plurality of second fins (70) delimited by the first and second recesses (66, 69) in the second layer are formed, the second fins (70) having a second pitch being narrower than the first pitch.
  4. The method according to claim 3, wherein the second pitch is half of the first pitch.
  5. The method according to claim 1, further comprising passivating or coating the ridges of the first layer (53) by an oxide, nitride or gas phase doping before the first dry etching process, in order to increase the etch selectivity.
  6. The method according to claim 3, further comprising passivating or coating the ridges of the second layer by an oxide, nitride or gas phase doping before the second dry etching process.

Description

Technical field The present invention relates to selective etching of nanostructures. Background The interest in manufacturing devices, e.g. advanced semiconductor devices, having dimensions below 100 nm have for the last decades been growing. Today a lateral size of advanced semiconductor devices, i.e. electronic components such as transistors, is already at and even below 20 nm. However, fabrication of structures with lateral size below 20 nm is hard to achieve with present processes. For instance, the spatial resolution of ultraviolet lithography, UVL, which is commonly used for manufacturing semiconductor devices in industry, is limited. Therefore, alternative novel approaches are required to overcome such challenges and to allow fabrication of nanostructures with lateral size below 20 nm. FR3009430 discloses a method for producing a pattern in an integrated circuit. At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench. US2008318032 discloses a method for patterning a material during fabrication of a semiconductor device. The method provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.JP2015023060 discloses a method of manufacturing a semiconductor device, capable of manufacturing a nanowire transistor including nanowires with a fine width and a narrow interval. The method of manufacturing a semiconductor device includes following steps of: forming a first mask extending in a first direction on a semiconductor layer; etching the semiconductor layer by using the first mask to form a convex first region having both lateral faces along the first direction and to form a second mask on both the lateral faces; removing the first mask to expose an upper surface in the first region; and etching the exposed upper surface to form second and third regions extending along the first direction, from the first region. JP2015023060 discloses a method of manufacturing a semiconductor device, capable of manufacturing a nanowire transistor including nanowires with a fine width and a narrow interval. The method of manufacturing a semiconductor device includes following steps of: forming a first mask extending in a first direction on a semiconductor layer; etching the semiconductor layer by using the first mask to form a convex first region having both lateral faces along the first direction and to form a second mask on both the lateral faces; removing the first mask to expose an upper surface in the first region; and etching the exposed upper surface to form second and third regions extending along the first direction, from the first region. According to Jonas Sundqvist ET AL: "Why do we need Atomic Layer Etching?", 10 January 2016 modern electronics requires atomic precision control and one of the main limitations in further electronic device downscaling is in precise material etching control. Atomic Layer Etching, ALE, technique provides a unique etching capability with atomic precision and minimal device damage. The ALE has been developed for few important materials such as Si, GaAs, GaInAs, AlInAs. However, plenty of materials yet to be explored, especially 2D materials such Graphene, MoS2 . It is also important to extend this technique to process nanowires and nanotubes. Nanowires are especially interesting for research at Lund Nano Lab and ALE capability for nanowires may open new research opportunities in Lund. Fabrication of stamps for nanoimprint may be another important field of ALE application in Lund Nano Lab. Though this ALE technique has impressive features for monolayer etching, several challenges are not solved yet. Hence, there are ample of scopes to work with. US 2015/318180 discloses a method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor, FinFET. The method includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the